JAJS190F March   2006  – May 2017

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Battery Preconditioning
      2. 7.3.2  Battery Fast-Charge Constant Current
      3. 7.3.3  Charge-Current Monitor
      4. 7.3.4  Battery Fast-Charge Voltage Regulation
      5. 7.3.5  Charge Termination Detection and Recharge
      6. 7.3.6  Charge Status Outputs
      7. 7.3.7  PG Output (bq24080)
      8. 7.3.8  Charge-Enabled (CE) Input (bq24080)
      9. 7.3.9  Timer Enabled (TE) Input (bq24081)
      10. 7.3.10 Temperature Qualification (bq24081)
      11. 7.3.11 Timer Fault and Recovery
        1. 7.3.11.1 Condition Number 1
        2. 7.3.11.2 Condition Number 2
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculations
        2. 8.2.2.2 Battery Temperature Sense (bq24081)
        3. 8.2.2.3 STAT Pins (All Devices) and PG Pin (bq24080)
        4. 8.2.2.4 Selecting Input and Output Capacitors
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Guidelines
      2. 10.1.2 Layout Example
      3. 10.1.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout

Layout Guidelines

Layout Guidelines

It is important to pay special attention to the PCB layout. The following provides some guidelines:

  • To obtain optimal performance, the decoupling capacitor from VCC to V(IN) and the output filter capacitors from OUT to VSS should be placed as close as possible to the device, with short trace runs to both signal and VSS pins. The VSS pin should have short trace runs to the GND pin.
  • All low-current VSS connections should be kept separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating both the small-signal ground path and the power ground path.
  • The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces.
  • The device is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application report entitled, QFN/SON PCB Attachment
    (TI Literature Number SLUA271).

Layout Example

bq24080 bq24081 layout_sluscb6.gif Figure 13. Board Layout

Thermal Considerations

The bq24080 and bq24081 are packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design guidelines for this package are provided in the application report entitled, QFN/SON PCB Attachment (TI Literature Number SLUA271).

The most common measure of package thermal performance is thermal impedance (RθJA) measured (or modeled) from the device junction to the air surrounding the package surface (ambient). The mathematical expression for RθJA is:

Equation 11. bq24080 bq24081 q5_viset_lus698.gif

Where:

  • TJ = device junction temperature
  • TA = ambient temperature
  • P = device power dissipation

Factors that can greatly influence the measurement and calculation of RθJA include:

  • Orientation of the device (horizontal or vertical)
  • Volume of the ambient air surrounding the device under test and airflow
  • Whether other surfaces are in close proximity to the device being tested
  • Use multiple 10–13 mil vias in the PowerPAD™ to copper ground plane.
  • Avoid cutting the ground plane with a signal trace near the power IC.
  • The PCB must be sized to have adequate surface area for heat dissipation.
  • FR4 (figerglass) thickness should be minimized.

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal Power FET. It can be calculated from the following equation:

Equation 12. bq24080 bq24081 q_power_lus698.gif

Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. See Figure 6.