SLUSBY7 July   2014

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dynamic Power Path Management
      2. 8.3.2 Production Test Mode
      3. 8.3.3 AnyBoot Battery Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1  Charge Profile
      2. 8.4.2  EN1/EN2 Pins
      3. 8.4.3  I2C Operation (Host Mode / Default Mode)
      4. 8.4.4  External Settings: ISET, ILIM and VIN_DPM
      5. 8.4.5  Transient Response
      6. 8.4.6  Input Voltage Based DPM
      7. 8.4.7  Sleep Mode
      8. 8.4.8  Input Over-Voltage Protection
      9. 8.4.9  NTC Monitor
      10. 8.4.10 Safety Timer
      11. 8.4.11 Watchdog Timer
      12. 8.4.12 Thermal Regulation and Thermal Shutdown
      13. 8.4.13 Fault Modes
      14. 8.4.14 Serial Interface Description
        1. 8.4.14.1 F/S Mode Protocol
    5. 8.5 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Board Layout
    3. 11.3 Package Summary
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

  1. Place the BOOT, PMID, IN, BAT, and LDO capacitors as close as possible to the IC for optimal performance.
  2. Connect the inductor as close as possible to the SW pin, and the SYS cap as close as possible to the inductor minimizing noise in the path.
  3. Place a 1-μF PMID capacitor as close as possible to the PMID and PGND pins, making the high frequency current loop area as small as possible.
  4. The local bypass capacitor from SYS to GND must be connected between the SYS pin and PGND of the IC. This minimizes the current path loop area from the SW pin through the LC filter and back to the PGND pin.
  5. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do not place components such that routing interrupts power-stage currents). All small control signals must be routed away from the high-current paths.
  6. To reduce noise coupling, use a ground plane if possible, to isolate the noisy traces from spreading its noise all over the board. Put vias inside the PGND pads for the IC.
  7. The high-current charge paths into IN, Micro-USB, BAT, SYS, and from the SW pins must be sized appropriately for the maximum charge current to avoid voltage drops in these traces.
  8. For high-current applications, the balls for the power paths must be connected to as much copper in the board as possible. This allows better thermal performance because the board conducts heat away from the IC.

11.2 Board Layout

layout_SLUSBR6.pngFigure 32. Recommended bq24250C PCB Layout for WCSP Package

11.3 Package Summary

topside_markings_SLUSBY7.gif

The bq24250C device is available in a 30-bump chip scale package (YFF, NanoFree™). The package dimensions are:

D – 2.427mm ±0.035mm

E – 2.027mm ±0.035mm