SLUS920A Data sheet

SLUS920A July 2009 – July 2015

PRODUCTION DATA.

11 Layout

It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
The control stage and the power stage should be routed separately. At each layer, the signal ground and the power ground are connected only at the thermal pad.
The AC current-sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact. The area of this loop must be minimized. An additional 0.1-μF decoupling capacitor for ACN is required to further reduce noise. The decoupling capacitors for these pins should be placed as close to the IC as possible.
The charge-current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact. The area of this loop must be minimized. An additional 0.1-μF decoupling capacitor for SRN is required to further reduce noise. The decoupling capacitors for these pins should be placed as close to the IC as possible.
Decoupling capacitors for PVCC (pin 28), VREF (pin 10), REGN (pin 24) should be placed underneath the IC (on the bottom layer) with the interconnections to the IC as short as possible.
Decoupling capacitors for BAT (pin 17), IADAPT (pin 15) must be placed close to the corresponding IC pins with the interconnections to the IC as short as possible.
Decoupling capacitor CX for the charger input must be placed close to the Q4 drain and Q5 source.

Figure 42 shows the recommended component placement with trace and via locations.

For VQFN information, refer to the following links: SCBA017 and SLUA271.

Figure 42. PCB Layout Layers