JAJSIG0A January   2020  – February 2022 BQ25616

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On-Reset (POR)
      2. 9.3.2 Device Power Up From Battery Without Input Source
      3. 9.3.3 Power Up From Input Source
        1. 9.3.3.1 Power Up ACFET
        2. 9.3.3.2 Power Up REGN LDO
        3. 9.3.3.3 Poor Source Qualification
        4. 9.3.3.4 Input Source Type Detection (IINDPM Threshold)
          1. 9.3.3.4.1 D+/D– Detection Sets Input Current Limit
        5. 9.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        6. 9.3.3.6 Power Up Converter in Buck Mode
      4. 9.3.4 Boost Mode Operation From Battery
      5. 9.3.5 Standalone Charger
      6. 9.3.6 Power Path Management
        1. 9.3.6.1 Narrow VDC Architecture
        2. 9.3.6.2 Dynamic Power Management
        3. 9.3.6.3 Supplement Mode
      7. 9.3.7 Battery Charging Management
        1. 9.3.7.1 Autonomous Charging Cycle
        2. 9.3.7.2 Battery Charging Profile
        3. 9.3.7.3 Charging Termination
        4. 9.3.7.4 Thermistor Qualification
          1. 9.3.7.4.1 JEITA Guideline Compliance During Charging Mode (BQ25616J)
          2. 9.3.7.4.2 Hot/Cold Temperature Window During Charging Mode (BQ25616)
          3. 9.3.7.4.3 Boost Mode Thermistor Monitor During Battery Discharge Mode
        5. 9.3.7.5 Charging Safety Timer
      8. 9.3.8 Status Outputs ( PG, STAT)
        1. 9.3.8.1 Power Good Indicator ( PG Pin )
        2. 9.3.8.2 Charging Status Indicator (STAT)
      9. 9.3.9 Protections
        1. 9.3.9.1 Input Current Limit
        2. 9.3.9.2 Voltage and Current Monitoring in Buck Mode
          1. 9.3.9.2.1 Input Overvoltage Protection (ACOV)
          2. 9.3.9.2.2 System Overvoltage Protection (SYSOVP)
        3. 9.3.9.3 Voltage and Current Monitoring in Boost Mode
          1. 9.3.9.3.1 Boost Mode Overvoltage Protection
        4. 9.3.9.4 Thermal Regulation and Thermal Shutdown
          1. 9.3.9.4.1 Thermal Protection in Buck Mode
          2. 9.3.9.4.2 Thermal Protection in Boost Mode
        5. 9.3.9.5 Battery Protection
          1. 9.3.9.5.1 Battery Overvoltage Protection (BATOVP)
          2. 9.3.9.5.2 Battery Overdischarge Protection
          3. 9.3.9.5.3 System Overcurrent Protection
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 BQ25616/616J Application without External OVP
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Inductor Selection
          2. 10.2.1.2.2 Input Capacitor and Resistor
          3. 10.2.1.2.3 Output Capacitor
        3. 10.2.1.3 Application Curves
      2. 10.2.2 BQ25616/616J Application with External OVP
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IQ_BAT  Quiescent battery current (BAT, SYS, SW) VBAT = 4.5V, VBUS floating or VBUS = 0V - 5V, SCL, SDA = 0V or 1.8V, TJ < 85 °C, BATFET on. 9.5 15 µA
IVBUS Input current (VBUS) in buck mode when converter is switching VBUS=5V, charge disabled, converter switching, ISYS = 0A 2.3 mA
IBST  Quiescent battery current (BAT, SYS, SW) in boost mode when converter is switching VBAT = 4.5V, VBUS = 4.9V, boost mode enabled, converter switching, IVBUS = 0A 2.4 mA
VBUS / VBAT SUPPLY
VVBUS_OP VBUS operating range 4 13.5 V
VVAC_UVLOZ VAC rising for ACFET turnon, no battery VAC rising 3.55 3.85 V
VVAC_UVLO VAC falling for ACFET turnoff, no battery VAC falling 3.25 3.55 V
VACDRV External ACFET gate drive voltage with minimum 8nF CGS 10 V
VVBUS_UVLOZ VBUS rising for active bias, no battery VBUS rising 3.3 3.7 V
VVBUS_UVLO VBUS falling to turnoff bias, no battery VBUS falling 3 3.3 V
VVBUS_PRESENT VBUS to enable REGN VBUS rising 3.65 3.9 V
VVBUS_PRESENTZ VBUS to disable REGN VBUS falling 3.15 3.4 V
VSLEEP Enter Sleep mode threshold VBUS falling, VBUS - VBAT, VBAT = 4V 15 60 110 mV
VSLEEPZ Exit Sleep mode threshold VBUS rising, VBUS - VBAT, VBAT = 4V 115 220 340 mV
VACOV VAC overvoltage rising threshold to turnoff ACFET and switching VAC rising 13.5 14.2 14.85 V
VAC overvoltage falling threshold to turnon ACFET and switching VAC falling, 13 13.9 14.5 V
VBAT_UVLOZ BAT voltage for active bias, no VBUS VBAT rising 2.5 V
VBAT_DPLZ BAT depletion rising threshold to turn on BATFET VBAT rising 2.35 2.8 V
VBAT_DPL BAT depletion falling threshold to turn off BATFET VBAT falling 2.18 2.62 V
VPOORSRC Bad adapter detection threshold VBUS falling 3.75 3.9 4.0 V
POWER PATH MANAGEMENT
VSYS_MIN Typical minimum system regulation voltage VBAT=3.2V < SYS_MIN = 3.5V, ISYS = 0A 3.5 3.65 V
VSYS_OVP System overvoltage threshold VREG = 4.35V, Charge disabled, ISYS = 0A 4.7 V
RON_RBFET Blocking FET on-resistance 45 mΩ
RON_HSFET High-side switching FET on-resistance 62 mΩ
RON_LSFET Low-side switching FET on-resistance 71 mΩ
VBATFET_FWD BATFET forward voltage in supplement mode BAT discharge current 10mA, converter running 30 mV
BATTERY CHARGER
VREG_ACC Charge voltage accuracy VREG = 4.1V, RVSET=10kΩ, TJ = 0°C - 85°C 4.0836 4.1 4.1164 V
VREG = 4.2V, RVSET>50kΩ, TJ = 0°C - 85°C 4.1832 4.2 4.2168 V
VREG = 4.35V, RVSET<500Ω, TJ = 0°C - 85°C 4.3326 4.35 4.3674 V
ICHG_RANGE  Typical charge current regulation range 0 3 A
KICHG ICHG pin setting ratio ICHG=KICHG/RICHG, VBAT = 3.1V, TJ = –40°C - 85°C 639 677 715 AxΩ
ICHG=KICHG/RICHG, VBAT = 3.8V, TJ = –40°C - 85°C 639 677 715 AxΩ
ICHG_ACC Fast charge current regulation accuracy RICHG = 1100 Ω, VBAT = 3.1V or 3.8V, TJ = –40°C - 85°C 0.516 0.615 0.715 A
RICHG = 562 Ω, VBAT = 3.1V or 3.8V, TJ = –40°C - 85°C 1.14 1.205 1.28 A
RICHG = 372 Ω, VBAT = 3.1V or 3.8V, TJ = –40°C - 85°C 1.715 1.82 1.89 A
IPRECHG_RATIO Precharge current accuracy As percentage of ICHG, VBAT = 2.6V 5 %
IPRECHG_ACC  Precharge current accuracy RICHG = 1100 Ω, VBAT = 2.6V, TJ = –40°C - 85°C 21 30 38 mA
RICHG = 562 Ω, VBAT = 2.6V, TJ = –40°C - 85°C 48 60 67 mA
RICHG = 372 Ω, VBAT = 2.6V, TJ = –40°C - 85°C 76 90 97 mA
ITERM_RATIO Termination current accuracy As percentage of ICHG, VBAT = 4.35V, (char, all codes) 5 %
ITERM_ACC Termination current accuracy RICHG = 1100 Ω, VBAT = 4.35V, TJ = 0°C - 85°C 9 31 57 mA
RICHG = 562 Ω, VBAT = 4.35V, TJ = 0°C - 85°C 36 60 85 mA
RICHG = 372 Ω, VBAT = 4.35V, TJ = 0°C - 85°C 56 91 126 mA
VBAT_SHORTZ Battery short voltage rising threshold to start pre-charge VBAT rising 2.13 2.25 2.35 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling 1.85 2 2.15 V
IBAT_SHORT Battery short trickle charging current VBAT < VBAT_SHORTZ 70 90 110 mA
VBATLOWV Battery LOWV rising threshold to start fast-charge VBAT rising 3 3.12 3.24 V
Battery LOWV falling threshold to stop fast-charge VBAT falling 2.7 2.8 2.9 V
VRECHG  Battery recharge threshold VBAT falling 90 100 150 mV
ISYS_LOAD System discharge load current during SYSOVP 30 mA
RON_BATFET Battery FET on-resistance TJ = -40°C - 85°C 19.5 26 mΩ
TJ = -40°C - 125°C 19.5 30 mΩ
BATTERY OVERVOLTAGE PROTECTION
VBAT_OVP Battery overvoltage rising threshold VBAT rising, as percentage of VREG 103 104 105 %
Battery overvoltage falling threshold VBAT falling, as percentage of VREG 101 102 103 %
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_ACC  Typical input voltage regulation accuracy 4.171 4.3 4.429 V
VINDPM_TRACK  VINDPM threshold to track battery voltage VBAT = 4.35V 4.45 4.55 4.74 V
IINDPM_ACC Input current regulation accuracy IINDPM = 500mA (TJ=-40°C - 85°C) 450 465 500 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 900mA (TJ=-40°C-85°C) 750 835 900 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 1500mA (TJ=-40°C-85°C) 1300 1390 1500 mA
KILIM ILIM pin setting ratio 459 478 500 A x Ω
D+ / D- DETECTION
VDP_SRC D+ line source voltage  500 600 700 mV
IDP_SRC D+ line data contact detect current source VD+ = 200 mV 7 10 14 µA
IDP_SINK D+ line sink current VD+ = 500 mV 50 100 150 µA
VDP_DAT_REF D+ line data detect voltage D+ pin Rising 250 400 mV
VDP_LGC_LOW D+ line logic low.  D+ pin Rising 800 mV
RDP_DWN D+ line pull-down resistance VD+ = 500 mV 14.25 24.8 kΩ
ID+_LKG Leakage current into D+ line Pull up to 1.8 V –1 1 µA
VDM_SRC D- line source voltage  500 600 700 mV
IDM_SINK D- line sink current VD- = 500 mV 50 100 150 µA
VDM_DAT_REF D- line data detect voltage D- pin Rising 250 400 mV
RDM_DWN D- line pull-down resistance VD- = 500 mV 14.25 24.8 kΩ
ID-_LKG Leakage current into D- line Pull up to 1.8 V –1 1 µA
VD+ _2p8_hi D+ High comparator threshold for 2.8V detection D+ pin rising 2.85 3 3.1 V
VD+ _2p8_lo D+ Low comparator threshold for 2.8V detection D+ pin rising 2.35 2.45 2.55 V
VD+ _2p8 D+ comparator threshold for non-standard adapter 2.55 2.85 V
VD- _2p8_hi D- High comparator threshold for 2.8V detection D- pin rising  2.85 3 3.1 V
VD- _2p8_lo D- Low comparator threshold for 2.8V detection D- pin rising 2.35 2.45 2.55 V
VD- _2p8 D- comparator threshold for non-standard adapter 2.55 2.85 V
VD+ _2p0_hi D+ High comparator threshold for 2.0V detection D+ pin rising 2.15 2.25 2.35 V
VD+ _2p0_lo D+ Low comparator threshold for 2.0V detection D+ pin rising 1.6 1.7 1.85 V
VD+ _2p0 D+ comparator threshold for non-standard adapter 1.85 2.15 V
VD- _2p0_hi D- High comparator threshold for 2.0V detection D- pin rising 2.15 2.25 2.35 V
VD- _2p0_lo D- Low comparator threshold for 2.0V detection D- pin rising 1.6 1.7 1.85 V
VD- _2p0 D- comparator threshold for non-standard adapter 1.85 2.15 V
VD+ _1p2_hi D+ High comparator threshold for 1.2V detection D+ pin rising 1.35 1.5 1.6 V
VD+ _1p2_lo D+ Low comparator threshold for 1.2V detection D+ pin rising 0.85 0.95 1.05 V
VD+ _1p2 D+ comparator threshold for non-standard adapter 1.05 1.35 V
VD- _1p2_hi D- High comparator threshold for 1.2V detection D- pin rising 1.35 1.5 1.6 V
VD- _1p2_lo D- Low comparator threshold for 1.2V detection D- pin rising 0.85 0.95 1.05 V
VD- _1p2 D- comparator threshold for non-standard adapter 1.05 1.35 V
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy 110 °C
TSHUT Thermal Shutdown Rising threshold Temperature Increasing 150 °C
Thermal Shutdown Falling threshold Temperature Decreasing 130 °C
CHARGE MODE THERMISTOR COMPARATOR (JEITA 616J or HOT/COLD 616)
VT1_RISE% TS pin voltage rising threshold, Charge suspended above this voltage. As Percentage to REGN (0°C w/ 103AT) 72.4 73.3 74.2 %
VT1_FALL% TS pin voltage falling threshold. Charge re-enabled to 20% of ICHG and VREG below this
voltage. 		 As Percentage to REGN 71.5 72 72.5 %
VT2_RISE % TS pin voltage rising threshold, Charge back to 20% of ICHG and VREG above this voltage (616J).  As Percentage to REGN (10°C w/ 103AT) 67.75 68.25 68.75 %
VT2_FALL% TS pin voltage falling threshold. Charge back to ICHG and VREG below this voltage (616J) As Percentage to REGN 66.45 66.95 67.45 %
VT3_FALL% TS pin voltage falling threshold. Charge back to ICHG and VREG below this voltage (616J) As Percentage to REGN (45°C w/ 103AT) 44.25 44.75 45.25 %
VT3_RISE% TS pin voltage rising threshold. Charge back to ICHG and VREG above this voltage. (616J) As Percentage to REGN  45.55 46.05 46.55 %
VT5_FALL% TS pin voltage falling threshold, charge suspended below this voltage.  As Percentage to REGN (60°C w/ 103AT) 33.7 34.2 35.1 %
VT5_RISE% TS pin voltage rising threshold. Charge back to ICHG and 4.1V above this voltage.  As Percentage to REGN 35 35.5 36 %
VT1_RISE_HC% TS pin voltage rising threshold. Charge suspended above this voltage. (616) As Percentage to REGN (0°C w/ 103AT) 72.4 73.3 74.2 %
VT1_FALL_HC% TS pin voltage falling threshold. Charge back to ICHG and VREG  below this voltage. (616) As Percentage to REGN 71 72 73 %
VT3_FALL_HC% TS pin voltage falling threshold.  Charge suspended below this voltage.  (616) As Percentage to REGN (45°C w/ 103AT) 44.25 44.75 45.25 %
VT3_RISE _HC% TS pin voltage rising threshold. Charge back to ICHG and VREG above this voltage. (616) As Percentage to REGN 45.55 46.05 46.55 %
BOOST MODE THERMISTOR COMPARATOR (HOT/COLD)
VBCOLD_RISE% TS pin voltage rising threshold, boost mode is suspended above this voltage.  As Percentage to REGN (–19.5°C w/ 103AT) 79.5 80 80.5 %
VBCOLD_FALL% TS pin voltage falling threshold As Percentage to REGN (0°C w/ 103AT) 72 %
VBHOT_FALL% TS pin voltage threshold. boost mode is suspended below this voltage.  As Percentage to REGN, (64°C w/ 103AT) 30.2 31.2 32.2 %
VBHOT_RISE% TS pin voltage rising threshold As Percentage to REGN, (45°C w/ 103AT) 44 %
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
IHSFET_OCP HSFET cycle-by-cycle overcurrent threshold 5.2 8.0 A
SWITCHING CONVERTER
FSW PWM switching frequency Oscillator frequency 1.32 1.5 1.68 MHz
DMAX Maximum PWM Duty Cycle 97 %
BOOST MODE CONVERTER
VBATLOWV_OTG Battery voltage exiting boost mode VVBAT falling 2.6 2.8 2.9 V
Battery voltage entering boost mode VVBAT rising 2.9 3.0 3.15 V
VBST_ACC Boost mode voltage regulation accuracy IVBUS = 0A, BOOST_V = 5V 4.85 5 5.15 V
IBST_ACC  Boost mode current regulation accuracy 1.2 1.4 1.6 A
ISYS_OCP_Q4 Boost mode battery discharge current clamp on BATFET Q4 9 10 A
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.58 4.7 4.8 V
VVBUS = 9V, IREGN = 20mA 5.6 6 6.5 V
IREGN REGN LDO current limit VVBUS = 5V, VREGN = 3.8V 50 mA
LOGIC INPUT PIN
VIH Input high threshold level (/CE) 1.3 V
VIL  Input low threshold level (/CE) 0.4 V
IIN_BIAS  High-level leakage current (/CE) Pull up rail 1.8V 1 µA
LOGIC OUTPUT PIN
VOL Output low threshold level (STAT, /PG) Sink current = 5mA 0.4 V
IOUT_BIAS High-level leakage current (STAT, /PG) Pull up rail 1.8V 1 µA