JAJSCJ1 October   2016

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Protection Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power Up
      2. 8.3.2 Battery Switch (Q1 + Q2)
      3. 8.3.3 Integrated 10-bit ADC for Monitoring
      4. 8.3.4 Linear Regulation Mode (LDO)
      5. 8.3.5 Protection Features
        1. 8.3.5.1 Reverse Current Protection (RCP)
        2. 8.3.5.2 Internal Thermal Shutdown
        3. 8.3.5.3 IBUS and VBUS Protection
        4. 8.3.5.4 IBAT and VBAT Protection
        5. 8.3.5.5 VOUT Protection
        6. 8.3.5.6 VDROP Protection
        7. 8.3.5.7 VBUS Temperature (TS_BUS_FLT) and Battery Temperature (TS_BAT_FLT)
      6. 8.3.6 I2C Serial Interface
        1. 8.3.6.1 Data Validity
        2. 8.3.6.2 START and STOP Conditions
        3. 8.3.6.3 Byte Format
        4. 8.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.6.5 Slave Address and Data Direction bit
        6. 8.3.6.6 Multi-Read and Multi-Write
    4. 8.4 Device Functional Modes
    5. 8.5 I2C Register Maps
      1. 8.5.1  I2C Register Summary Table
      2. 8.5.2  REG00 (DEVICE_INFO)
      3. 8.5.3  REG01 (EVENT_1_MASK)
      4. 8.5.4  REG02 (EVENT_2_MASK)
      5. 8.5.5  REG03 (EVENT_1)
      6. 8.5.6  REG04 (EVENT_2)
      7. 8.5.7  REG05 (EVENT_1_EN)
      8. 8.5.8  REG06 (CONTROL)
      9. 8.5.9  REG07 (ADC_CONTROL)
      10. 8.5.10 REG08 (ADC_EN)
      11. 8.5.11 REG09 (PROTECTION)
      12. 8.5.12 REG0A (VBUS_OVP)
      13. 8.5.13 REG0B (VOUT_REG)
      14. 8.5.14 REG0C (VDROP_OVP)
      15. 8.5.15 REG0D (VDROP_ALM)
      16. 8.5.16 REG0E (VBAT_REG)
      17. 8.5.17 REG0F (IBAT_REG)
      18. 8.5.18 REG10 (IBUS_REG)
      19. 8.5.19 REG11 (TS_BUS_FLT)
      20. 8.5.20 REG12 (TS_BAT_FLT)
      21. 8.5.21 REG 13 and REG 14 (VBUS_ADC)
      22. 8.5.22 REG15 and REG16 (IBUS_ADC)
      23. 8.5.23 REG17 and REG18 (VOUT_ADC)
      24. 8.5.24 REG19 and REG1A (VDROP_ADC)
      25. 8.5.25 REG1B and REG1C (VBAT_ADC)
      26. 8.5.26 REG1D and REG1E (IBAT_ADC)
      27. 8.5.27 REG1F and REG20 (TS_BUS_ADC)
      28. 8.5.28 REG21 and REG22 (TS_BAT_ADC)
      29. 8.5.29 REG 23 (TDIE_ADC)
      30. 8.5.30 REG 24 (EVENT_2_EN)
      31. 8.5.31 REG 25 (EVENT_3_MASK)
      32. 8.5.32 REG 26 (EVENT_3)
      33. 8.5.33 REG 29 (CONTROL_2)
      34. 8.5.34 REG 40 (DIE_TEMP_FLT)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

bq25871 supports up to 7-A charge current. It is very critical to maximize Cu trace of VBUS and VOUT. Following PCB layout guideline is recommended:

  • Use Cu trace of at least 110 mil (2.794 mm) wide for VBUS and VOUT respectively. This allows current flow evenly through all 7 WCSP solder balls.
  • Cu trace of VBUS and VOUT should run at least 150 mil (3.81 mm) straight (perpendicular to WCSP ball array) before making turns.
  • Use as large as possible Cu pour for VBUS and VOUT trace elsewhere.
  • Use as large as possible Cu pour for PGND.
  • Place decoupling capacitors of VBUS and VOUT as close as possible to the device.

11.2 Layout Example

bq25871 layout1_luscn1.gif Figure 61. bq25871 Layout Diagram (Top Layer)
bq25871 layout2_luscn1.gif Figure 62. bq25871 Layout Diagram (Mid Layer 2)
bq25871 layout3_luscn1.gif Figure 63. bq25871 Layout Diagram (Mid Layer 1)
bq25871 layout4_luscn1.gif Figure 64. bq25871 Layout Diagram (Bottom 1)