JAJSOR2L August   1998  – September 2023 CD4051B , CD4052B , CD4053B

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Parameter Measurement Information

GUID-1CA402A2-517C-4AF1-9522-2B758B4BC5D2-low.gif Figure 7-1 Typical Bias Voltages
Note:

The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS
and 1 = VDD. The analog signal (through the TG) may swing from VEE to VDD.

GUID-4FB4ACE1-364B-4BDA-B6C0-6D9F2863B6DD-low.gifFigure 7-2 Waveforms, Channel Being Turned ON (RL = 1 kΩ)
GUID-343706FB-9C11-4944-A23E-C729BC6D9D7A-low.gifFigure 7-3 Waveforms, Channel Being Turned OFF (RL = 1 kΩ)
GUID-7C1AF540-3190-4997-AF0B-0C6A20EA6D9A-low.gif Figure 7-4 OFF Channel Leakage Current – Any Channel OFF
GUID-EEB9A72F-46B2-4AEA-A3AE-47E31054692B-low.gif Figure 7-5 On Channel Leakage Current – Any Channel On
GUID-C08E6182-7848-40B7-B7CB-F77C5BA0EE3E-low.gif Figure 7-6 OFF Channel Leakage Current – All Channels OFF
GUID-E9415111-5E4B-4A2E-A58D-3AD867D3E377-low.gif Figure 7-7 Propagation Delay – Address Input to Signal Output
GUID-F26870EE-C080-450A-8623-07C5F4C7B3F7-low.gif Figure 7-8 Propagation Delay – Inhibit Input to Signal Output
GUID-139C8AB7-57C8-42ED-8FE1-98BECD2AE9B2-low.gif Figure 7-9 Input Voltage Test Circuits (Noise Immunity)
GUID-31DE5B26-5B08-4400-A8B8-DB66F4960CF5-low.gifFigure 7-10 Quiescent Device Current
GUID-88F7EB06-5634-4A0D-A0DF-F02D277E7807-low.gifFigure 7-11 Channel ON Resistance Measurement Circuit
GUID-5CC20AE1-B319-49BC-B38C-C053F89368F0-low.gif Figure 7-12 Input Current
GUID-9ECA13C5-9021-42A0-BCA0-B67D75263BD1-low.gifFigure 7-13 Feed-Through (All Types)
GUID-AB6C39AC-EB77-4D7A-A895-50B41ED8BBA8-low.gifFigure 7-14 Crosstalk Between Any Two Channels (All Types)
GUID-268A5251-1CE1-4DC8-B40F-2329FE3663CB-low.gif Figure 7-15 Crosstalk Between Duals or Triplets (CD4052B, CD4053B)
GUID-60E47EB2-D7C2-41FD-BA7F-62D39C6FCF1A-low.gif
Special Considerations: In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or CD4053B.
Figure 7-16 Typical Time-Division Application of the CD4052B
GUID-D78AC8AF-24AD-45E0-B6B9-CC620FD37553-low.gif Figure 7-17 24-to-1 MUX Addressing