JAJSU06A December   1998  – March 2024 CD54AC374 , CD54ACT374 , CD74AC374 , CD74AC534 , CD74ACT374

PRODUCTION DATA  

  1.   1
  2. 特長
  3. 概要
  4. Pin Configuration and Functions
  5. Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions:
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: AC Series
    6. 4.6  Electrical Characteristics: ACT Series
    7. 4.7  Prerequisite for Switching: AC Series
    8. 4.8  Switching Characteristics: AC Series
    9. 4.9  Prerequisite for Switching: ACT Series
    10. 4.10 Switching Characteristics: ACT Series
  6. Parameter Measurement Information
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Design Requirements
      2. 7.1.2 Detailed Design Procedure
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • J|20
サーマルパッド・メカニカル・データ

Overview

The eight flip-flops of the ’AC374 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The RCA-CD54/74AC374 and CD54/74AC534 and the CD54/74ACT374 and CD54/74ACT534 octal D-type, 3-state, positive-edge triggered flip-flops use the RCA ADVANCED CMOS technology. The eight flip-flops enter data into their registers on the LOW-to-HIGH transition of the clock (CP). The Output Enable (OE) controls the 3-state outputs and is independent of the register operation. When the Output Enable (OE) is HIGH, the outputs are in the high-impedance state. The CD54/74AC/ACT374 and CD54/74AC/ACT534 share the same pin configurations, but the CD54/74AC/ACT374 outputs are non-inverted while the CD54/74AC/ACT534 devices have inverted outputs. (For flow-through pin configurations, see CD54/74AC/ACT564 and CD54/74AC/ACT574.)

The CD74AC/ACT374 and CD74AC/ACT534 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commercial (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54AC/ACT374 and CD54AC/ACT534, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.