JAJSOA6D November   1998  – March 2022 CD54HC251 , CD54HCT251 , CD74HC251 , CD74HCT251

PRODUCTION DATA  

  1. 特長
  2. 説明
  3. Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • N|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

Overview

The ’HC251 and ’HCT251 are 8-channel digital multiplexers with three-state outputs, fabricated with high-speed silicongate CMOS technology. Together with the low power consumption of standard CMOS integrated circuits, they possess the ability to drive 10 LSTTL loads. The three-state feature makes them ideally suited for interfacing with bus lines in a bus-oriented system.

This multiplexer features both true (Y) and complement (Y) outputs as well as an output enable (OE) input. The OE must be at a low logic level to enable this device. When the OE input is high, both outputs are in the high-impedance state. When enabled, address information on the data select inputs determines which data input is routed to the Y and Y outputs. The ’HCT251 logic family is speed, function, and pin-compatible with the standard ’LS251.