JAJSOC9F November   1997  – March 2022 CD54HC4094 , CD74HC4094 , CD74HCT4094

PRODUCTION DATA  

  1. 1 特長
  2. 2 説明
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • NS|16
  • N|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

7.3 Device Functional Modes

Table 7-1 Truth Table
Inputs(2)Parallel OutputsSerial Outputs
CPOESTRDQ0QnQS1(1)QS2
↑LXXZZQ6NC
↓LXXZZNCQ7
↑HLXNCNCQ6NC
↑HHLLQn – 1Q6NC
↑HHHHQn – 1Q6NC
↓HHHNCNCNCQ7
(1) At the positive clock edge the information in the seventh register stage is transferred to the eighth register stage and QS1 output.
(2) H = High voltage level, L = Low voltage level, X = Don't care, NC = No charge, Z = High-impedance off−state, ↑ = Transition from low-to-high level, ↓ = Transition from high to low.