JAJSO86F November   1998  – March 2022 CD54HC173 , CD54HCT173 , CD74HC173 , CD74HCT173

PRODUCTION DATA  

  1. 特長
  2. 概要
  3. Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Prerequisite For Switching Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • N|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

Parameter Measurement Information

tPD is the maximum between tPLH and tPHL

tt is the maximum between tTLH and tTHL

GUID-E341EDCD-3F84-4FDC-BDB7-2FA9725152A3-low.png

NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%

Figure 6-1 HC clock pulse rise and fall times and pulse width
GUID-DCDCCB23-16A9-4304-986E-DC64878B7AE6-low.pngFigure 6-3 HC and HCU transition times and propagation delay times, combination logic
GUID-5EA3EE1F-B241-4414-B8F4-98DF133A59F7-low.pngFigure 6-5 HC setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits
GUID-6E7712E6-4641-483E-9EC9-B3F719788E2B-low.pngFigure 6-7 HC three-state propagation delay waveform
GUID-DF955312-9977-42A4-8419-8A4F5B0E9082-low.png

NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. FOr fMAX, input duty cycle = 50%

Figure 6-2 HCT clock pulse rise and fall times and pulse width
GUID-7259891A-F304-4436-AA2C-0EACAA60E528-low.pngFigure 6-4 HCT transition times and propagation delay times, combination logic
GUID-FD8333F7-8880-4DB7-8A98-D078DBA71B3B-low.pngFigure 6-6 HCT setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits
GUID-6B991D1D-965E-4CAD-BC8E-113B4D70215A-low.pngFigure 6-8 HCT three-state propagation delay waveform
GUID-2869F2D8-7738-486A-91A6-E647CE67F916-low.png

NOTE: Opend drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF

Figure 6-9 HC and HCT three-state propagation delay test circuit