SCAS884D August   2009  – December 2015 CDCLVP1102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: LVCMOS Input
    6. 6.6 Electrical Characteristics: Differential Input
    7. 6.7 Electrical Characteristics: LVPECL Output
    8. 6.8 Electrical Characteristics: LVPECL Output
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Fanout Buffer for Line Card Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

7.1 Test Configurations

This section describes the function of each block for the CDCLVP1102. Figure 3 through Figure 9 illustrate how the device should be setup for a variety of test configurations.

CDCLVP1102 ai_test_lvcmos_dc_in_cas884.gif Figure 3. DC-Coupled LVCMOS Input During Device Test
CDCLVP1102 ai_vth_var_lvcmos_in_cas884.gif Figure 4. Vth Variation Over LVCMOS Levels
CDCLVP1102 ai_test_lvpecl_dc_in_cas884.gif Figure 5. DC-Coupled LVPECL Input During Device Test
CDCLVP1102 ai_test_lvds_dc_in_cas884.gif Figure 6. DC-Coupled LVDS Input During Device Test
CDCLVP1102 ai_test_diff_ac_in_cas884.gif Figure 7. AC-Coupled Differential Input to Device
CDCLVP1102 ai_test_lvpecl_dc_out_cas884.gif Figure 8. LVPECL Output DC Configuration During Device Test
CDCLVP1102 ai_test_lvpecl_ac_out_cas884.gif Figure 9. LVPECL Output AC Configuration During Device Test

Figure 10 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 11.

CDCLVP1102 ai_vo_tr_tf_cas884.gif Figure 10. Output Voltage and Rise/Fall Time
CDCLVP1102 ai_vo_skew_cas884.gif
1. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn (n = 0, 1), or as the difference between the fastest and the slowest tPHLn (n = 0, 1).
2. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn (n = 0, 1) across multiple devices, or the difference between the fastest and the slowest tPHLn (n = 0, 1) across multiple devices.
Figure 11. Output and Part-to-Part Skew