SLPS264D October   2010  – May 2015 CSD86330Q3D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Power Loss Curves
    2. 6.2 Safe Operating Curves (SOA)
    3. 6.3 Normalized Curves
    4. 6.4 Calculating Power Loss and SOA
      1. 6.4.1 Design Example
      2. 6.4.2 Calculating Power Loss
      3. 6.4.3 Calculating SOA Adjustments
  7. 7Recommended PCB Design Overview
    1. 7.1 Electrical Performance
    2. 7.2 Thermal Performance
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q3D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation
    4. 9.4 Q3D Tape and Reel Information

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発注情報

7 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief description on how to address each parameter is provided.

7.1 Electrical Performance

The Power Block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.

  • The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34). The example in Figure 34 uses 6 × 10 µF ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8 should follow in order.
  • The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for the Driver IC will also connect to this pin.
  • The switching node of the output inductor should be placed relatively close to the Power Block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level.
  • In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a Boost Resistor or RC snubber can be an effective way to reduce the peak ring level. The recommended Boost Resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of Driver IC used in conjunction with the Power Block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Refer to TI App Note SLUP100 for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND see Figure 34(1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

7.2 Thermal Performance

The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10 mil drill hole and a 16 mil capture pad.
  • Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

CSD86330Q3D layout1.pngFigure 34. Recommended PCB Layout (Top Down)