SLPS542 January   2015 CSD97394Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
  7. 7 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powering CSD97394Q4M And Gate Drivers
      2. 8.3.2 Undervoltage Lockout Protection (UVLO)
      3. 8.3.3 PWM Pin
      4. 8.3.4 SKIP# Pin
        1. 8.3.4.1 Zero Crossing (ZX) Operation
      5. 8.3.5 Integrated Boost-Switch
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application Curves
  10. 10System Example
    1. 10.1 Power Loss Curves
    2. 10.2 Safe Operating Curves (SOA)
    3. 10.3 Normalized Curves
      1. 10.3.1 Calculating Power Loss and SOA
        1. 10.3.1.1 Design Example
        2. 10.3.1.2 Calculating Power Loss
        3. 10.3.1.3 Calculating SOA Adjustments
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Recommended PCB Design Overview
      2. 11.1.2 Electrical Performance
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Recommended PCB Land Pattern
    3. 13.3 Recommended Stencil Opening

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DPC|8
サーマルパッド・メカニカル・データ
発注情報

12 Device and Documentation Support

12.1 Trademarks

NexFET is a trademark of Texas Instruments.

Windows is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.