SNAS348G May   2006  – April 2016 DAC124S085

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Output Amplifiers
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Input Shift Register
      3. 8.5.3 DSP or Microprocessor Interfacing
        1. 8.5.3.1 ADSP-2101 or ADSP2103 Interfacing
        2. 8.5.3.2 80C51 or 80L51 Interface
        3. 8.5.3.3 68HC11 Interface
      4. 8.5.4 Microwire Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Bipolar Operation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4132
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Supply voltage, VA 6.5 V
Voltage on any input pin –0.3 6.5 V
Input current at any pin(4) 10 mA
Package input current(4) 20 mA
Power consumption at TA = 25°C See(5)
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin must be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation is reached only when the device is operated in a severe fault condition (that is, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Machine model (MM) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VA Supply voltage 2.7 5.5 V
VREFIN Reference voltage 1 VA V
Digital input voltage(2) 0 5.5 V
Output load 0 1500 pF
SCLK frequency 40 MHz
TA Operating temperature –40 105 °C
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(2) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, do not cause errors in the conversion result. For example, if VA is 3 V, the digital input pins can be driven with a 5-V logic device.
DAC124S085 20173204.gif

7.4 Thermal Information

THERMAL METRIC(1) DAC124S085 UNIT
DGS (VSSOP) DSC (WSON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 240 250 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.3 40.7 °C/W
RθJB Junction-to-board thermal resistance 78.9 23.7 °C/W
ψJT Junction-to-top characterization parameter 4.8 0.4 °C/W
ψJB Junction-to-board characterization parameter 77.6 23.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 4.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
STATIC PERFORMANCE
Resolution –40°C ≤ TA ≤ 105°C 12 Bits
Monotonicity –40°C ≤ TA ≤ 105°C 12 Bits
INL Integral non-linearity TA = 25°C ±2.4 LSB
–40°C ≤ TA ≤ 105°C ±8
DNL Differential non-linearity VA = 2.7 V to 5.5 V TA = 25°C ±0.2 LSB
–40°C ≤ TA ≤ 105°C –0.5 0.7
VA = 4.5 V to 5.5 V(2) TA = 25°C ±0.15 LSB
–40°C ≤ TA ≤ 105°C ±0.5
ZE Zero code error IOUT = 0 mA TA = 25°C 4 mV
–40°C ≤ TA ≤ 105°C 15
FSE Full-scale error IOUT = 0 mA TA = 25°C –0.1% FSR
–40°C ≤ TA ≤ 105°C –0.75%
GE Gain error All ones loaded
to DAC register		 TA = 25°C –0.2% FSR
–40°C ≤ TA ≤ 105°C –1%
ZCED Zero code error drift –20 µV/°C
TC GE Gain error tempco VA = 3 V –0.7 ppm/°C
VA = 5 V –1 ppm/°C
OUTPUT CHARACTERISTICS
Output voltage range(2) –40°C ≤ TA ≤ 105°C 0 VREFIN V
IOZ High-impedance output leakage current(2) –40°C ≤ TA ≤ 105°C ±1 µA
ZCO Zero code output VA = 3 V, IOUT = 200 µA 1.3 mV
VA = 3 V, IOUT = 1 mA 6 mV
VA = 5 V, IOUT = 200 µA 7 mV
VA = 5 V, IOUT = 1 mA 10 mV
FSO Full-scale output VA = 3 V, IOUT = 200 µA 2.984 V
VA = 3 V, IOUT = 1 mA 2.934 V
VA = 5 V, IOUT = 200 µA 4.989 V
VA = 5 V, IOUT = 1 mA 4.958 V
IOS Output short-circuit current (source) VA = 3 V, VOUT = 0 V, Input Code = FFFh –56 mA
VA = 5 V, VOUT = 0 V, Input Code = FFFh –69 mA
IOS Output short-circuit current (sink) VA = 3 V, VOUT = 3 V, Input Code = 000h 52 mA
VA = 5 V, VOUT = 5 V, Input Code = 000h 75 mA
IO Continuous output current(2) Available on each DAC output,
–40°C ≤ TA ≤ 105°C		 11 mA
CL Maximum load capacitance RL = ∞ 1500 pF
RL = 2 kΩ 1500 pF
ZOUT DC output impedance 7.5 Ω
REFERENCE INPUT CHARACTERISTICS
VREFIN(3) Input range minimum TA = 25°C 0.2 V
–40°C ≤ TA ≤ 105°C 1
Input range maximum –40°C ≤ TA ≤ 105°C VA V
Input impedance 30 kΩ
LOGIC INPUT CHARACTERISTICS
IIN Input current(2) –40°C ≤ TA ≤ 105°C ±1 µA
VIL Input low voltage(2) VA = 3 V TA = 25°C 0.9 V
–40°C ≤ TA ≤ 105°C 0.6
VA = 5 V TA = 25°C 1.5 V
–40°C ≤ TA ≤ 105°C 0.8
VIH Input high voltage(2) VA = 3 V TA = 25°C 1.4 V
–40°C ≤ TA ≤ 105°C 2.1
VA = 5 V TA = 25°C 2.1 V
–40°C ≤ TA ≤ 105°C 2.4
CIN Input capacitance(2) –40°C ≤ TA ≤ 105°C 3 pF
POWER REQUIREMENTS
VA(3) Supply voltage minimum –40°C ≤ TA ≤ 105°C 2.7 V
Supply voltage maximum –40°C ≤ TA ≤ 105°C 5.5 V
IN Normal supply current fSCLK = 30 MHz,
output unloaded,
VA = 2.7 V to 3.6 V		 TA = 25°C 360 µA
–40°C ≤ TA ≤ 105°C 485
fSCLK = 30 MHz,
output unloaded,
VA = 4.5 V to 5.5 V		 TA = 25°C 480 µA
–40°C ≤ TA ≤ 105°C 650
fSCLK = 0 MHz, output unloaded, VA = 2.7 V to 3.6 V 330 µA
fSCLK = 0 MHz, output unloaded, VA = 4.5 V to 5.5 V 440 µA
IPD Power-down supply current(2) All PD modes,
output unloaded,
SYNC = DIN = 0 V
after PD mode loaded,
VA = 2.7 V to 3.6 V		 TA = 25°C 0.1 µA
–40°C ≤ TA ≤ 105°C 1
All PD modes,
output unloaded,
SYNC = DIN = 0 V
after PD mode loaded,
VA = 4.5 V to 5.5 V		 TA = 25°C 0.15 µA
–40°C ≤ TA ≤ 105°C 1
PN Normal supply power fSCLK = 30 MHz,
output unloaded,
VA = 2.7 V to 3.6 V		 TA = 25°C 1.1 mW
–40°C ≤ TA ≤ 105°C 1.7
fSCLK = 30 MHz,
output unloaded,
VA = 4.5 V to 5.5 V		 TA = 25°C 2.4 mW
–40°C ≤ TA ≤ 105°C 3.6
fSCLK = 0 MHz,
output unloaded		 VA = 2.7V to 3.6 V 1 mW
VA = 4.5 V to 5.5 V 2.2 mW
PPD Power-down supply power(2) All PD modes, output unloaded,
SYNC = DIN = 0 V
after PD mode loaded		 VA = 2.7 V to 3.6 V 0.3 3.6 µW
VA = 4.5 V to 5.5 V 0.8 5.5 µW
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
(3) To ensure accuracy, it is required that VA and VREFIN be well bypassed.

7.6 Timing Requirements

TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
fSCLK SCLK frequency TA = 25°C 40 MHz
–40°C ≤ TA ≤ 105°C 30
ts Output voltage settling time(2) 400h to C00h
code change
RL = 2 kΩ, CL = 200 pF		 TA = 25°C 6 µs
–40°C ≤ TA ≤ 105°C 8.5
SR Output slew rate 1 V/µs
Glitch impulse Code change from 800h to 7FFh 12 nV-sec
Digital feedthrough 0.5 nV-sec
Digital crosstalk 1 nV-sec
DAC-to-DAC crosstalk 3 nV-sec
Multiplying bandwidth VREFIN = 2.5 V ± 0.1 Vpp 160 kHz
Total harmonic distortion VREFIN = 2.5 V ± 0.1 Vpp
input frequency = 10 kHz		 70 dB
tWU Wake-up time VA = VREF = 3 V 6 µs
VA = VREF = 5 V 39 µs
1/fSCLK SCLK cycle time TA = 25°C 25 ns
–40°C ≤ TA ≤ 105°C 33
tCH SCLK high time TA = 25°C 7 ns
–40°C ≤ TA ≤ 105°C 10
tCL SCLK low time TA = 25°C 7 ns
–40°C ≤ TA ≤ 105°C 10
tSS SYNC set-up time
prior to SCLK falling edge		 TA = 25°C 4 ns
–40°C ≤ TA ≤ 105°C 10
tDS Data set-up time
prior to SCLK falling edge		 TA = 25°C 1.5 ns
–40°C ≤ TA ≤ 105°C 3.5
tDH Data hold time
after SCLK falling edge		 TA = 25°C 1.5 ns
–40°C ≤ TA ≤ 105°C 3.5
tCFSR SCLK fall
prior to rise of SYNC		 TA = 25°C 0 ns
–40°C ≤ TA ≤ 105°C 3
tSYNC SYNC high time TA = 25°C 6 ns
–40°C ≤ TA ≤ 105°C 10
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
DAC124S085 20173205.gif Figure 1. Input and Output Transfer Characteristic
DAC124S085 20173206.gif Figure 2. Serial Timing Diagram

7.7 Typical Characteristics

TA = 25°C, VREF = VA, fSCLK = 30 MHz, and input code range 48 to 4047 (unless otherwise noted)
DAC124S085 20173252.png Figure 3. INL at VA = 3 V
DAC124S085 20173254.png Figure 5. DNL at VA = 3 V
DAC124S085 20173256.png Figure 7. INL/DNL vs VREFIN
at VA = 3 V
DAC124S085 20173250.png Figure 9. INL/DNL vs fSCLK
at VA = 2.7 V
DAC124S085 20173224.png Figure 11. INL/DNL vs Clock Duty Cycle
at VA = 3 V
DAC124S085 20173226.png Figure 13. INL/DNL vs Temperature
at VA = 3 V
DAC124S085 20173230.png Figure 15. Zero Code Error vs VA
DAC124S085 20173234.png Figure 17. Zero Code Error vs fSCLK
DAC124S085 20173236.png Figure 19. Zero Code Error vs Temperature
DAC124S085 20173232.png Figure 21. Full-Scale Error vs VREFIN
DAC124S085 20173238.png Figure 23. Full-Scale Error vs Clock Duty Cycle
DAC124S085 20173244.png Figure 25. Supply Current vs VA
DAC124S085 20173246.png Figure 27. 5-V Glitch Response
DAC124S085 20173253.png Figure 4. INL at VA = 5 V
DAC124S085 20173255.png Figure 6. DNL at VA = 5 V
DAC124S085 20173257.png Figure 8. INL/DNL vs VREFIN
at VA = 5 V
DAC124S085 20173222.png Figure 10. INL/DNL vs VA
DAC124S085 20173225.png Figure 12. INL/DNL vs Clock Duty Cycle
at VA = 5 V
DAC124S085 20173227.png Figure 14. INL/DNL vs Temperature
at VA = 5 V
DAC124S085 20173231.png Figure 16. Zero Code Error vs VREFIN
DAC124S085 20173235.png Figure 18. Zero Code Error vs Clock Duty Cycle
DAC124S085 20173237.png Figure 20. Full-Scale Error vs VA
DAC124S085 20173233.png Figure 22. Full-Scale Error vs fSCLK
DAC124S085 20173239.png Figure 24. Full-Scale Error vs Temperature
DAC124S085 20173245.png Figure 26. Supply Current vs Temperature
DAC124S085 20173247.png Figure 28. Power-On Reset