SLAS646C December   2009  – May 2015 DAC3282

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - DC Specifications
    6. 6.6 Electrical Characteristics - AC Specifications
    7. 6.7 Electrical Characteristics - Digital Specifications
    8. 6.8 Timing Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input FIFO
      2. 7.3.2  FIFO Alarms
      3. 7.3.3  FIFO Modes of Operation
      4. 7.3.4  Dual Sync Sources Mode
      5. 7.3.5  Single Sync Source Mode
      6. 7.3.6  Bypass Mode
      7. 7.3.7  Data Pattern Checker
      8. 7.3.8  FIR Filters
      9. 7.3.9  Coarse Mixer
      10. 7.3.10 Digital Offset Control
      11. 7.3.11 Temperature Sensor
      12. 7.3.12 Sleep Modes
      13. 7.3.13 Reference Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Data Interface
      2. 7.4.2 LVPECL Inputs
      3. 7.4.3 LVDS Inputs
      4. 7.4.4 CMOS Digital Inputs
      5. 7.4.5 DAC Transfer Function
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  CONFIG0 (address = 0x00) [reset = 0x70]
      2. 7.6.2  CONFIG1 (address = 0x01) [reset = 0x11]
      3. 7.6.3  CONFIG2 (address = 0x02) [reset = 0x00]
      4. 7.6.4  CONFIG3 (address = 0x03) [reset = 0x10]
      5. 7.6.5  CONFIG4 (address = 0x04) [reset = 0xFF]
      6. 7.6.6  CONFIG5 (address = 0x05) READ ONLY
      7. 7.6.7  CONFIG6 (address =0x06) [reset = 0x00]
      8. 7.6.8  CONFIG7 (address = 0x07) [reset = 0x00] (WRITE TO CLEAR)
      9. 7.6.9  CONFIG8 (address = 0x08) [reset = 0x00] (WRITE TO CLEAR)
      10. 7.6.10 CONFIG9 (address = 0x09) [reset = 0x7A]
      11. 7.6.11 CONFIG10 (address = 0x0A) [reset = 0xB6]
      12. 7.6.12 CONFIG11 (address = 0x0B) [reset = 0xEA]
      13. 7.6.13 CONFIG12 (address =0x0C) [reset = 0x45]
      14. 7.6.14 CONFIG13 (address =0x0D) [reset = 0x1A]
      15. 7.6.15 CONFIG14 Register Name (address = 0x0E) [reset = 0x16]
      16. 7.6.16 CONFIG15 Register Name (address = 0x0F) [reset = 0xAA]
      17. 7.6.17 CONFIG16 (address = 0x10) [reset = 0xC6]
      18. 7.6.18 CONFIG17 (address = 0x11) [reset = 0x00]
      19. 7.6.19 CONFIG18 (address = 0x12) [reset = 0x02]
      20. 7.6.20 CONFIG19 (address = 0x13) [reset = 0x00]
      21. 7.6.21 CONFIG20 (address = 0x14) [reset = 0x00] (CAUSES AUTOSYNC)
      22. 7.6.22 CONFIG21 (address = 0x15) [reset = 0x00]
      23. 7.6.23 CONFIG22 (address = 0x16) [reset = 0x00]
      24. 7.6.24 CONFIG23 (address = 0x17) [reset = 0x00]
      25. 7.6.25 CONFIG24 (address = 0x18) [reset = 0x83]
      26. 7.6.26 CONFIG25 (address = 0x19) [reset = 0x00]
      27. 7.6.27 CONFIG26 (address = 0x1A) [reset = 0x00]
      28. 7.6.28 CONFIG27 (address =0x1B) [reset = 0x00]
      29. 7.6.29 CONFIG28 (address = 0x1C) [reset = 0x00]
      30. 7.6.30 CONFIG29 (address = 0x1D) [reset = 0x00]
      31. 7.6.31 CONFIG30 (address = 0x1E) [reset = 0x00]
      32. 7.6.32 VERSION31 (address = 0x1F) [reset = 0x43] (READ ONLY)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multi-device Synchronization
        1. 8.1.1.1 Multi-device Synchronization: Dual Sync Sources Mode
        2. 8.1.1.2 Multi-device Operation: Single Sync Source Mode
      2. 8.1.2 Analog Current Outputs
      3. 8.1.3 Passive Interface to Analog Quadrature Modulators
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-up Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Definition Of Specifications
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage DACVDD18(2) –0.5 2.3 V
DIGVDD18(2) –0.5 2.3
CLKVDD18(2) –0.5 2.3
VFUSE(2) –0.5 2.3
AVDD33(2) –0.5 4
Terminal voltage CLKVDD18 to DIGVDD18 –0.5 0.5 V
DACVDD18 to DIGVDD18 –0.5 0.5
D[7..0]P ,D[7..0]N, DATACLKP,DATACLKN, FRAMEP, FRAMEN(2) –0.5 DIGVDD18 + 0.5
DACCLKP, DACCLKN, OSTRP, OSTRN(2) –0.5 CLKVDD18 + 0.5
ALARM_SDO, SDIO, SCLK, SDENB, RESETB, TXENABLE(2) –0.5 DIGVDD18 + 0.5
IOUTA1/B1, IOUTA2/B2(2) –1.0 AVDD33 + 0.5
EXTIO, BIASJ(2) –0.5 AVDD33 + 0.5
Peak input current (any input) 20 mA
Peak total input current (all inputs) –30 mA
TA Operating free-air temperature, DAC3282 –40 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to GND.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Voltage 1.8-V DAC core supply voltage, DACDVDD18 1.7 1.8 1.9 V
1.8-V digital supply voltage, DIGVDD18 1.7 1.8 1.9 V
1.8-V internal clock buffer supply voltage, CLKVDD18 1.7 1.8 1.9 V
3.3-V analog supply voltage, AVDD33 3.0 3.3 3.6 V

6.4 Thermal Information

THERMAL METRIC(1) DAC3282 UNIT
RGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 26.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 12.2 °C/W
RθJB Junction-to-board thermal resistance 3.7 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 3.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics – DC Specifications(1)

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 Bits
DC ACCURACY
DNL Differential nonlinearity 1 LSB = IOUTFS/216 ±2 LSB
INL Integral nonlinearity ±4 LSB
ANALOG OUTPUT
Coarse gain linearity ±0.04 LSB
Offset error Mid code offset 0.01 %FSR
Gain error With external reference ±2 %FSR
With internal reference ±2 %FSR
Gain mismatch With internal reference –2 2 %FSR
Minimum full scale output current Nominal full-scale current, IOUTFS = 16 × IBIAS current. 2 mA
Maximum full scale output current 20
Output compliance range(2) IOUTFS = 20 mA AVDD –0.5V AVDD +0.5V V
Output resistance 300 kΩ
Output capacitance 5 pF
REFERENCE OUTPUT
VREF Reference output voltage 1.14 1.2 1.26 V
Reference output current(3) 100 nA
REFERENCE INPUT
VEXTIO Input voltage range External Reference Mode 0.1 1.2 1.25 V
Input resistance 1 MΩ
Small signal bandwidth 472 kHz
Input capacitance 100 pF
TEMPERATURE COEFFICIENTS
Offset drift ±1 ppm of FSR/°C
Gain drift With external reference ±15 ppm of FSR/°C
With internal reference ±30
Reference voltage drift ±8 ppm/°C
POWER SUPPLY
AVDD33 3.0 3.3 3.6 V
DACVDD18, DIGVDD18, CLKVDD18 1.7 1.8 1.9 V
I(AVDD33) Analog supply current Mode 1(below) 96 mA
I(DIGVDD18) Digital supply current 268 mA
I(DACVDD18) DAC supply current 74 mA
I(CLKVDD18) Clock supply current 10 mA
I(AVDD33) Power down mode analog supply current Mode 4 (below) 2 mA
I(DIGVDD18) Power down mode digital supply current 3 mA
I(DACVDD18) Power down mode DAC supply current 0.5 mA
I(CLKVDD18) Power down mode clock supply current 1 mA
P Power Dissipation Mode 1: fDAC = 625MSPS, 2x interpolation, mixer on,
Digital Offset Control on		 950 1100 mW
Mode 2: fDAC = 491.52MSPS, 2x interpolation, Zero-IF
Correction Filter on, mixer off, Digital Offset Control on		 845 mW
Mode 3: Sleep Mode, fDAC = 625MSPS, 2X interpolation, mixer on,
DAC in sleep mode:
CONFIG24 sleepa, sleepb set to 1		 575 mW
Mode 4: Power-Down mode, No clock, static data pattern, DAC in power-down mode:
CONFIG23 clkpath_sleep_a, clkpath_sleepb set to 1
CONFIG24 clkrecv_sleep, sleepa, sleepb set to 1 		15 mW
PSRR Power Supply Rejection Ratio DC tested –0.4 0.4 %/FSR/V
T Operating Range –40 25 85 °C
(1) Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25 Ω each to AVDD.
(2) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC3282 device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(3) Use an external buffer amplifier with high impedance input to drive any external load.

6.6 Electrical Characteristics – AC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT(1)
fDAC Maximum output update rate 1x Interpolation 312.5 MSPS
2x Interpolation 625
Digital Latency No interpolation, FIFO off, Offset off, Inverse sinc off 38 DAC clock cycles
2x Interpolation 59
Zero-IF Sinc Correction Filter 16
FIFO 8
Offset 4
AC PERFORMANCE(2)
SFDR Spurious Free Dynamic Range SFDR (0 to fDAC/2) Tone at 0 dBFS fDAC = 625 MSPS, fOUT = 10.1 MHz 2x Interp, DAC A+B on 83 dBc
fDAC = 625 MSPS, fOUT = 20.1 MHz 2x Interp, DAC A+B on 78
fDAC = 625 MSPS, fOUT = 70.1 MHz 2x Interp, DAC A+B on 64
IMD3 Third-order two-tone intermodulation distortion Each tone at –6 dBFS fDAC = 625 MSPS, fOUT = 30 ± 0.5 MHz 2x Interp, DAC A+B on 82 dBc
fDAC = 625 MSPS, fOUT = 50 ± 0.5 MHz 2x Interp, DAC A+B on 80
fDAC = 625 MSPS, fOUT = 150 ± 0.5 MHz 2x Interp, DAC A+B on, 69
NSD Noise Spectral Density Single Tone at 0 dBm fDAC = 625 MSPS, fOUT = 10.1 MHz 2x Interp, DAC A+B on 161 dBc/Hz
fDAC = 625 MSPS, fOUT = 150.1 MHz 2x Interp, DAC A+B on 150
WCDMA(3) Adjacent Channel Leakage Ratio, Single Carrier fDAC = 491.52 MSPS, fOUT= 30.72 MHz 2x Interp, DAC A+B on 81 dBc
fDAC = 491.52 MSPS, fOUT = 153.6 MHz 2x Interp, DAC A+B on 76
Alternate Channel Leakage Ratio, Single Carrier fDAC = 491.52 MSPS, fOUT = 30.72 MHz 2x Interp, DAC A+B on 84 dBc
fDAC = 491.52 MSPS, fOUT = 153.6 MHz 2x Interp, DAC A+B on 77 dBc
Channel Isolation fDAC = 625 MSPS, fOUT = 10 MHz 84 dBc
(1) Measured single ended into 50 Ω load.
(2) 4:1 transformer output termination, 50 Ω doubly terminated load.
(3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms

6.7 Electrical Characteristics – Digital Specifications

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS INTERFACE: D[7:0]P/N, DATACLKP/N, FRAMEP/N(1)
fDATA Input data rate Byte-wide DDR format
DATACLK frequency = 625 MHz 		312.5 MSPS
fBUS Byte-wide LVDS data transfer rate 1x Interpolation 1250 MSPS
2x Interpolation 1250
VA,B+ Logic high differential input voltage threshold 175 400 mV
VA,B– Logic low differential input voltage threshold –175 –400 mV
VCOM Input Common Mode 1.0 1.2 2.0 V
ZT Internal termination 85 110 135 Ω
CL LVDS Input capacitance 2 pF
CLOCK INPUT (DACCLKP/N)
Duty cycle 40% 60%
Differential voltage(2) 0.4 1.0 V
DACCLKP/N Input Frequency 625 MHz
OUTPUT STROBE (OSTRP/N)
fOSTR Frequency fOSTR = fDACCLK / (n × 8 × Interp) where n is any positive integer fDACCLK is DACCLK frequency in MHz fDACCLK /
(8 x interp) 		MHz
Duty cycle 40% 60%
Differential voltage 0.4 1.0 V
CMOS INTERFACE: ALARM_SDO, SDIO, SCLK, SDENB, RESETB, TXENABLE
VIH High-level input voltage 1.25 V
VIL Low-level input voltage 0.54 V
IIH High-level input current –40 40 μA
IIL Low-level input current –40 40 μA
CI CMOS Input capacitance 2 pF
VOH SDO, SDIO Iload = –100 μA DIGVDD18 –0.2 V
SDO, SDIO Iload = –2 mA 0.8 x DIGVDD18 V
VOL SDO, SDIO Iload = 100 μA 0.2 V
SDO, SDIO Iload = 2 mA 0.5 V
(1) See LVDS INPUTS section for terminology.
(2) Driving the clock input with a differential voltage lower than 1 V will result in degraded performance.

6.8 Timing Characteristics

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT(1)
ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10.4 ns
tpd Output propagation delay DAC outputs are updated on the falling edge of DAC clock. Does not include Digital Latency (see below). 2 ns
tr(IOUT) Output rise time 10% to 90% 220 ps
tf(IOUT) Output fall time 90% to 10% 220 PS
Power-up time DAC Wake-up Time IOUT current settling to 1% of IOUTFS. Measured from SDENB rising edge; Register CONFIG24, toggle sleepa from 1 to 0 90 μs
DAC Sleep Time IOUT current settling to less than 1% of IOUTFS. Measured from SDENB rising edge; Register CONFIG24, toggle sleepa from 0 to 1. 90 μs
TIMING LVDS INPUTS: DATACLKP/N, double edge latching – See Figure 25
ts(DATA) Setup time, D[7:0]P/N and FRAMEP/N, valid to either edge of DATACLKP/N FRAMEP/N latched on rising edge of DATACLKP/N only 0 ps
th(DATA) Hold time, D[7:0]P/N and FRAMEP/N, valid after either edge of DATACLKP/N FRAMEP/N latched on rising edge of DATACLKP/N only 400 ps
t(FRAME) FRAMEP/N pulse width fDATACLK is DATACLK frequency in MHz 1/2fDATACLK ns
t_align Maximum offset between DATACLKP/N and DACCLKP/N rising edges FIFO Bypass Mode only
fDACCLK is DACCLK frequency in MHz		 1/2fDACCLK –0.55 ns
TIMING OSTRP/N Input: DACCLKP/N rising edge latching
ts(OSTR) Setup time, OSTRP/N valid to rising edge of DACCLKP/N 200 ps
th(OSTR) Hold time, OSTRP/N valid after rising edge of DACCLKP/N 200 ps
SERIAL PORT TIMING – See Figure 40 and Figure 41
ts(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns
ts(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns
th(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns
t(SCLK) Period of SCLK Register CONFIG5 read (temperature sensor read) 1 μs
All other registers 100 ns
t(SCLKH) High time of SCLK Register CONFIG5 read (temperature sensor read) 0.4 μs
All other registers 40 ns
t(SCLKL) Low time of SCLK Register CONFIG5 read (temperature sensor read) 0.4 μs
All other registers 40 ns
td(Data) Data output delay after falling edge of SCLK 10 ns
tRESET Minimum RESETB pulsewidth 25 ns

6.9 Typical Characteristics

DAC3282 INL_las646.gifFigure 1. Integral Non-Linearity
DAC3282 SFDR_fo_las646.gifFigure 3. SFDR vs Input Scale
DAC3282 SFDR3_fo_las646.gifFigure 5. SFDR vs fDAC
DAC3282 power_f_las646.gifFigure 7. Single Tone Spectral Plot
DAC3282 IMD3_fo_las646.gifFigure 9. IMD3 vs Input Scale
DAC3282 IMD3b_fo_las646.gifFigure 11. IMD3 vs fDAC
DAC3282 NSD_fo_las646.gifFigure 13. NSD vs Input Scale
DAC3282 NSD3_fo_las646.gifFigure 15. NSD vs fDAC
DAC3282 ACLR_fo_las646.gifFigure 17. Single Carrier WCDMA ACLR vs Input Scale
DAC3282 pwr_msps_las646.gifFigure 19. Power vs fDATA
DAC3282 DACVDD_fdac_las646.gifFigure 21. DACVDD18 vs fDAC
DAC3282 AVDD33_f_las646.gifFigure 23. AVDD33 vs fDAC
DAC3282 DNL_las646.gifFigure 2. Differential Non-Linearity
DAC3282 SFDR2_fo_las646.gifFigure 4. SFDR vs Interpolation
DAC3282 SFDR4_fo_las646.gifFigure 6. SFDR vs IOUTFS
DAC3282 power2_f_las646.gifFigure 8. Single Tone Spectral Plot
DAC3282 IMD3a_fo_las646.gifFigure 10. IMD3 vs Interpolation
DAC3282 IMD3c_fo_las646.gifFigure 12. IMD3 vs IOUTFS
DAC3282 NSD2_fo_las646.gifFigure 14. NSD vs Interpolation
DAC3282 NSD4_fo_las646.gifFigure 16. NSD vs IOUTFS
DAC3282 ACLR2_fo_las646.gifFigure 18. Four Carrier WCDMA ACLR vs Input Scale
DAC3282 DVDD18_f_las646.gifFigure 20. DVDD18 vs fDATA
DAC3282 CLKVDD18_fo_las646.gifFigure 22. CLKVDD18 vs fDAC