JAJSS39A November 2023 – March 2024 DAC39RF10EF , DAC39RFS10EF
PRODUCTION DATA
One of the major advantages of the DAC39RF10EF および RFS10EF in applications like Doppler radar, Quantum Computing and Wireless Test is the ability to directly synthesize very low phase noise signals all the way through X-band (12 GHz). To take full advantage of the exceptionally low additive phase noise of the DAC, a very high-performance clock is required.
Equally important in most systems is the impact of Size, Weight, Area, Power and Cost (SWAP-C). This means each system architect must weight tradeoffs in performance vs. overall system SWAP-C based on system requirements. In this section we present three clocking examples based on SWAP-C vs. performance tradeoffs.
Figure 8-6 below shows a plot of phase noise for an 8 GHz sample clock produced by an integrated PLL+VCO, integrated PLL with external high performance VCO and a fully discrete high performance analog PLL. All examples assume a reference clock is provided as an input to the synthesizer, which can range from low cost surface mount crystal oscillators all the way to very expense reference subsystems. The DAC39RF10EF および RFS10EF additive phase noise at 8 GHz is also provided for comparison - even for the analog PLL, the clock phase noise degrades the DAC39RF10EF および RFS10EF output phase noise for offset frequencies below 5 MHz.