JAJSLU6B May   2023  – March 2024 DAC39RF10 , DAC39RFS10

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Bandwidth and DC Linearity
    12. 6.12 Typical Characteristics: Single Tone Spectra
    13. 6.13 Typical Characteristics: Dual Tone Spectra
    14. 6.14 Typical Characteristics: Noise Spectral Density
    15. 6.15 Typical Characteristics: Linearity Sweeps
    16. 6.16 Typical Characteristics: Modulated Waveforms
    17. 6.17 Typical Characteristics: Phase and Amplitude Noise
    18. 6.18 Typical Characteristics: Power Dissipation and Supply Currents
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Eye Scan Procedure
      4. 8.1.4 Pre/Post Cursor Analysis Procedure
      5. 8.1.5 Understanding Dual Edge Sampling Modes
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
        1. 8.2.1.1 System Schematic
        2. 8.2.1.2 Design Requirements
        3. 8.2.1.3 Detailed Transmitter Design Procedure
        4. 8.2.1.4 Detailed Clocking Subsystem Design Procedure
          1. 8.2.1.4.1 Example 1: SWAP-C Optimized
          2. 8.2.1.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.1.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.1.4.4 10 GHz Clock Generation
        5. 8.2.1.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報
Example 3: Discrete Analog PLL for Best DAC Performance

When phase noise performance is paramount, a discrete analog PLL (APLL) offers substantially lower phase noise than the integrated examples. The trade off is increased SWAP-C. Figure 8-10 shows the block diagram of such an implementation that uses the same Synergy Microwave 8 GHz DRO as the LMX2820 external VCO example discussed previously.

GUID-20230306-SS0I-ZM98-F13J-7K6PFQTPSJPF-low.svgFigure 8-10 Discrete Analog PLL

The APLL outperforms the previous examples by avoiding use of digital dividers and phase detectors, which significantly degrade phase noise. Instead passive diode-based frequency multipliers and mixers are used, which contribute little additive phase noise. Like all synthesizers, a frequency reference with very good close in phase noise, below the loop bandwidth of the APLL, is required for best performance.

In this case, a 1 GHz reference was chosen as the reference is a convenient division of the sample rate and is available either as an output of an R&S SMA100B RF signal generator or as a standalone unit from Wenzel Associates.

As mentioned previously, the APLL does not use digital dividers or phase detectors, which significantly degrade phase noise. Instead the reference is multiplied up to the output frequency using passive multiplier stages (see Figure 8-11). A passive mixer is used as a phase detector that feeds a low noise operational amplifier loop filter. The DRO output is split with one output going to the DAC clock distribution network and the other feeding back into the RF port of the mixer.

GUID-20230306-SS0I-VCX7-PBJS-WPN9C1H8XN5R-low.svgFigure 8-11 Reference Multiplier Chain

The multiplier chain uses low noise amplifiers, passive diode multipliers and bandpass filters. For this part of the circuit, what is most critical is the close in phase noise below the loop bandwidth of the PLL. Not all amplifiers demonstrate good close in noise, especially when driven near or into compression. Generally, heterojunction bipolar transistor (HBT) amplifiers, have low flicker noise and operate well when driven into compression.

Bandpass filters were selected to remove the FIN and 3 x FIN/2 harmonics that are only partially suppressed by the multipliers. In some implementations the driving amplifier can be filtered to prevent degradation of the harmonic suppression performance. This chain was experimentally optimized, but additional attenuation between stages can be added to manage reflections and amplifier operating conditions.

The loop filter bandwidth is set near where the open loop DRO phase noise crosses the multiplied reference noise with a damping factor set to give a smooth role off that minimizes integrated phase noise. An optional additional feedback cap can be used to speed up the role off if desired (C2 is set roughly to 1/10th to 1/100th of C1). The loop filter component values were determined experimentally for this design.

In some implementations a start-up circuit is needed to help the loop acquire lock. In practice we found that the initial power up was all that was needed to get the loop enough of a kick to get the loop to pull in and lock.