JAJSS39A November   2023  – March 2024 DAC39RF10EF , DAC39RFS10EF

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
    6. 7.6 SPI Register Map
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Transmitter Design Procedure
        1. 8.2.3.1 Detailed Clocking Subsystem Design Procedure
          1. 8.2.3.1.1 Example 1: SWAP-C Optimized
          2. 8.2.3.1.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.3.1.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.3.1.4 10 GHz Clock Generation
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Power Supply Recommendations

The device has three supply voltages and requires seven supply domains to achieve data sheet performance as shown in Table 8-3:

Table 8-3 Recommended Power Supply Domains
Voltage Supply Domain Device Supplies
+1.8V VDDA VDDA18A, VDDA18B
VDDIO VDDIO
VDDCSR VDDCLK, VDDSYS, VDDR
+1.0V VDDL VDDLA, VDDLB
VDCCCLK VDDCLK10
DVDD VDDDIG, VDDT, VDDDEA & VDDDEB
-1.8V VEEx VEEAM18, VEEBM18

The recommended power supply is shown in Figure 8-22. The power-supply voltages must be low in noise and provide the needed current to achieve rated device performance. A step down high-efficiency switching converter is used first, followed by a second stage of regulation using LDOs to provide switching noise reduction and improved voltage accuracy. The user can also refer to the TI WEBENCH® Power Designer which can be used to select and design the individual power supply elements as needed. The recommended switching regulators are:

  • TPSM82913 = +2.3 V for the VDDA, VDDIO, VDDCSR, VDDL and VDCCCLK domains
  • TPS543620 = +1 V for DVDD
  • TPSM82913 = +3.8 V for VEEx domain

and recommended LDOs include:

  • TPS7A9401 for +1.8 V and +1 V
  • LM27762 for -1.8 V

GUID-20230419-SS0I-2K8K-6HXB-LZPMMDLQJHZB-low.svg Figure 8-22 Recommended Power Supply Block Diagram

The VDDA supply is regulated by an LDO, or low-noise drop-out linear regulator, with a +1.8 V output and is further broken down into the following subgroup power domains:

  • VDDA: VDDA18A, VDDA18B
  • VDDIO
  • VDDCSR: VDDCLK, VDDSYS, VDDR

Each device supply can be tied to a single LDO but are isolated with a ferrite bead and/or three-terminal capacitor or similar.

The VDDL supply is +1 V and is further broken down into VDDLA and VDDLB. Each device supply can be tied to a single LDO but are isolated with a ferrite bead and/or three-terminal capacitor or similar.

The VDDCLK10 supply is +1 V and is the most sensitive for achieving the best phase noise performance. VDDCLK10 should be isolated to a LDO by itself to prevent noise from other 1.0V supplies coupling into the clock path.

The DVDD supply is +1.0V and can be directly connected to a switching power supply. The DVDD encompasses the following device supplies, VDDDIG, VDDT, VDDDEA & VDDDEB, which can all be connected together. No further isolation with a ferrite bead and/or three-terminal capacitor or similar is required.

The VEEx supply is -1.8 V derived from a single LDO and is further broken down into VEEAM18 and VEEBM18, which are isolated with a ferrite bead and/or three-terminal capacitor or similar.

It is also highly recommended to follow these important power supply design considerations:

  1. Decouple all power supply rails and bus voltages as they come onto the system board. Further place additional decoupling at or near the DAC itself for each power domain. Typically, one decoupling capacitor per power supply pin is suffice unless specified in the data sheet or EVM assembly.
  2. Remember that approximately 20 dB/decade noise suppression is gained for each additional filtering stage.
  3. Decouple for both high and low frequencies, which might require multiple capacitor values.
  4. Series ferrite beads and feed through capacitors are commonly used at the power plain entry point and can be used for addition power domain isolation. This should be done for each individual supply voltage on the system board whether it comes from an LDO or a switching regulator.
  5. For added capacitance, use tightly stacked power and ground plane pairs (≤4 mil spacing) this adds inherent high-frequency (>500 MHz) decoupling to the PCB design.
  6. Keep supplies away from sensitive analog circuitry such as the front-end RF stage of the DAC and high-speed clocking and digital circuits if possible.
  7. Keep power domains that demand higher currents, near the top of the stack-up or layer that has power plain entry point. This minimizes the overall loop inductance.
  8. Any open or voided areas on power plane, fill with ground to provide additional isolation and shielding.
  9. Keep a 20 to 25 mil gap between all adjacent power and/or ground plane fills. This helps eliminate all gap coupling between adjacent power domains and/or grounds within the same layer.
  10. Some switcher regulator circuitry/components could be located on the opposite side of the PCB for added isolation.
  11. Follow the IC manufacture recommendations; if they are not directly stated in an application note or data sheet, then study the evaluation board. These are great vehicles to learn from. Applying these points above can help provide a solid power supply design yielding data sheet performance in many applications.

Each application has different tolerances for noise on the supply voltage, so understanding these trades is best described in the following two application notes for more details:

Also refer to Figure 8-30 through Figure 8-33 to illustrate the one power supply layout and stack-up approach.