JAJSHR1A
July 2019 – December 2019
DAC43401
,
DAC53401
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
機能ブロック図
DACx3401 による電源制御
4
改訂履歴
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements: I2CTM Standard mode
7.7
Timing Requirements: I2CTM Fast mode
7.8
Timing Requirements: I2CTM Fast+ mode
7.9
Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
7.10
Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
7.11
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Digital-to-Analog Converter (DAC) Architecture
8.3.1.1
Reference Selection and DAC Transfer Function
8.3.1.1.1
Power Supply as Reference
8.3.1.1.2
Internal Reference
8.3.2
DAC Update
8.3.2.1
DAC Update Busy
8.3.3
Nonvolatile Memory (EEPROM or NVM)
8.3.3.1
NVM Cyclic Redundancy Check
8.3.3.2
NVM_CRC_ALARM_USER Bit
8.3.3.3
NVM_CRC_ALARM_INTERNAL Bit
8.3.4
Programmable Slew Rate
8.3.5
Power-on-Reset (POR)
8.3.6
Software Reset
8.3.7
Device Lock Feature
8.3.8
PMBus Compatibility
8.4
Device Functional Modes
8.4.1
Power Down Mode
8.4.2
Continuous Waveform Generation (CWG) Mode
8.4.3
PMBus Compatibility Mode
8.4.4
Medical Alarm Generation Mode
8.4.4.1
Low-Priority Alarm
8.4.4.2
Medium-Priority Alarm
8.4.4.3
High-Priority Alarm
8.4.4.4
Interburst Time
8.4.4.5
Pulse Off Time
8.4.4.6
Pulse On Time
8.5
Programming
8.5.1
F/S Mode Protocol
8.5.2
DACx3401 I2C Update Sequence
8.5.3
Address Byte
8.5.4
Command Byte
8.5.5
I2C Read Sequence
8.6
Register Map
8.6.1
STATUS Register (address = D0h) (reset = 000Ch or 0014h)
Table 18.
STATUS Register Field Descriptions
8.6.2
GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)
Table 19.
GENERAL_CONFIG Register Field Descriptions
8.6.3
MED_ALARM_CONFIG Register (address = D2h) (reset = 0000h)
Table 20.
MED_ALARM_CONFIG Register Field Descriptions
8.6.4
TRIGGER Register (address = D3h) (reset = 0008h)
Table 21.
TRIGGER Register Field Descriptions
8.6.5
DAC_DATA Register (address = 21h) (reset = 0000h)
Table 22.
DAC_DATA Register Field Descriptions
8.6.6
DAC_MARGIN_HIGH Register (address = 25h) (reset = 0000h)
Table 23.
DAC_MARGIN_HIGH Register Field Descriptions
8.6.7
DAC_MARGIN_LOW Register (address = 26h) (reset = 0000h)
Table 24.
DAC_MARGIN_LOW Register Field Descriptions
8.6.8
PMBUS_OPERATION Register (address = 01h) (reset = 0000h)
Table 25.
PMBUS_OPERATION Register Field Descriptions
8.6.9
PMBUS_STATUS_BYTE Register (address = 78h) (reset = 0000h)
Table 26.
PMBUS_STATUS_BYTE Register Field Descriptions
8.6.10
PMBUS_VERSION Register (address = 98h) (reset = 2200h)
Table 27.
PMBUS_VERSION Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Programmable LED Biasing
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Power-Supply Margining
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
9.2.3
Medical Alarm Generation
9.2.3.1
Design Requirements
9.2.3.2
Detailed Design Procedure
9.2.3.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントのサポート
12.1.1
関連資料
12.2
関連リンク
12.3
ドキュメントの更新通知を受け取る方法
12.4
サポート・リソース
12.5
商標
12.6
静電気放電に関する注意事項
12.7
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DSG|8
MPDS308C
サーマルパッド・メカニカル・データ
DSG|8
QFND141I
発注情報
jajshr1a_oa
jajshr1a_pm
8.2
Functional Block Diagram