The DAC43901-Q1 and DAC43902-Q1 support state-machines preconfigured for sequential turn-indicator animation, as shown in Figure 7-7, Figure 7-8, and Figure 7-9. The fade-in is done logarithmically. Table 7-9 shows the pin multiplexing of the PWM channels and the programming interface. The PWM outputs are available on the digital pins in the standalone mode. The device goes into standalone mode when the VREF/MODE pin is pulled high. In this mode, the programming interface is disabled. The device functions per the configurations in the NVM. The digital programming interface (I²C and SPI) pins are open-drain outputs and must be pulled up to function as PWM outputs. Pulling the VREF/MODE pin low brings the device into programming mode. When the PWM output mode is enabled, all four programming interface pins act as PWM outputs, even if not used. Partial selection is not possible. The PWM duty-cycle resolution is 7 bits. The animation pattern is triggered by an external signal applied to the TRIG-IN pin or by controlling the power supply to the smart DAC. When more than four channels are required, multiple devices can be cascaded by daisy-chaining the TRIG-OUT (DAC43902-Q1 only) and the TRIG-IN pins, as shown in Figure 7-8. In some cases, the LED modules are in separate subsystems and there is no way to daisy-chain the device; the only common connection is the power. Figure 7-9 shows a configuration wherein the delay for the first channel in the following devices is configured to match the cumulative delay of all the channels in the predecessor devices. The timing diagram of the sequential turn-indicator animation is shown in Figure 7-10. The fade-in timing configurations are done as described in Section 7.4.2. The PWM frequency is configured as per Table 7-7.

Figure 7-7 Sequential Turn-Indicator Animation

Figure 7-8 Sequential Turn-Indicator Animation With Cascaded Devices

Figure 7-9 Sequential Turn-Indicator Animation Using Unconnected LED Modules

Figure 7-10 Sequential Turn-Indicator Animation Timing Diagram

Each PWM channel can be started after a delay with respect to the previous respective channel. Figure 7-10 shows that there is a separate delay for the first channel, PWM0, and then a common delay for other channels, including the TRIG-OUT pin. Equation 6 gives the SLEW-RATE calculation for DAC43902-Q1. Equation 5 gives the calculation for total fade-in time. The channel delays are a function of the SLEW-RATE, as given in Equation 4 and the delay settings, CH0-DELAY or COM-DELAY. Equation 7 is used to calculate the delay. CH0-DELAY defines the delay before starting the fade-in operation for PWM0, and COM-DELAY defines the delay before starting the fade-in for all other PWM channels, including the delay before toggling TRIG-OUT. The delay applies even when the fade-in is disabled by writing 0 for FADE-IN-RATE. In this case, a predefined delay setting of 256 is considered. The DAC43902-Q1 does not have the fade-out function.

where:

• t_{SLEW_RATE} is the fade-in unit time in microseconds/step.
• SLEW_RATE is the FADE-IN-RATE as specified in Table 7-10 for DAC43902-Q1.

where:

• t_DELAY is the delay before the fade-in operation for each channel in seconds.
• DELAY is the CH0-DELAY or COM-DELAY as specified in Table 7-10 for DAC43902-Q1 or as specified in Table 7-10 for DAC43901-Q1.
• t_SLEW is the unit slew rate calculated as per Equation 4.

Table 7-11 shows the list of register settings done for the device configuration.