SBAS721A December   2015  – January 2016 DAC60096

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DAC DC
    6. 6.6  Electrical Characteristics: Square-Wave Output
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics: DC Mode
    10. 6.10 Typical Characteristics: Toggle Mode
    11. 6.11 Typical Characteristics, General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converters (DACs)
        1. 7.3.1.1 DAC Transfer Function
        2. 7.3.1.2 DAC Register Structure
      2. 7.3.2 Reference Specifications
    4. 7.4 Device Functional Modes
      1. 7.4.1 Toggle Mode
      2. 7.4.2 DC Mode
    5. 7.5 Programming
      1. 7.5.1 Frame Error Checking
    6. 7.6 Register Maps
      1. 7.6.1 8.5.1 BUFA Register (address = 0x0) [reset = 0x0000]
      2. 7.6.2 BUFB Register (address = 0x1) [reset = 0x0000]
      3. 7.6.3 CON Register (address = 0x4) [reset = 0x0555]
      4. 7.6.4 CRC Register (address = 0x5) [reset = 0xFFF]
      5. 7.6.5 PTR Register (address = 0x6) [reset = 0x0000]
      6. 7.6.6 SWR Register (address = 0x7) [reset = 0x0000]
      7. 7.6.7 PWRM Register (address = 0x6) [reset = 0xCAFE]
      8. 7.6.8 SDIV Register (address = 0x9) [reset = 0x0000]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power-Supply Bypassing
        2. 8.2.2.2 Reference Input
        3. 8.2.2.3 TRIGG/Signal Conditioning
        4. 8.2.2.4 External Amplifier Selection
        5. 8.2.2.5 Unbuffered Settling Response
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Device Reset Options
      1. 9.1.1 Power-on-Reset (POR)
      2. 9.1.2 Hardware Reset
      3. 9.1.3 Software Reset
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Optimal Layout Example
      2. 10.2.2 Standard Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

  • Bypass all power-supply pins to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.1-µF to 0.22-µF ceramic with a X7R or NP0 dielectric.
  • Place power supplies and VREFH/L bypass capacitors close to pins to minimize inductance and optimize performance. Inner supply and reference pads can connect to the bypass arrangement on the bottom layer of the PCB through vias to minimize trace length. This is illustrated in Figure 56 and Figure 59.
  • Include a 100-nF bypass capacitor for both internal reference inputs between this pin and their respective ground pins.
  • Use a high-quality ceramic type NP0 or X7R for optimal performance across temperature, and low dissipation factor.
  • Make sure that the digital and analog sections have proper placement with respect to the digital pins and analog pins of the DAC60096 device. The separation of analog and digital blocks allow for better design and practice because it reduces coupling into neighboring blocks, and minimizes the interaction between analog and digital return currents.

10.2 Layout Examples

10.2.1 Optimal Layout Example

Optimal layout requires the addition of blind vias. This layout reduces trace length and brings the bypass capacitor arrangements closer to the device pads. Figure 56 to Figure 59 show the board layouts.

Figure 56. DAC60096 Example Board Layout – Top Layer PCB
Figure 57. DAC60096 Example Board Layout – Internal AVCC and AVSS Plane
Figure 58. DAC60096 Example Board Layout – DVDD Internal Plane With Select DAC Outputs
Figure 59. DAC60096 Example Board Layout – Bottom Layer PCB.
(A): Bypass Capacitor Arrangement; (B) Polygon Pours; (C) PAD With Pours

10.2.2 Standard Layout Example

Only through-hole vias are included in this layout. Bypass capacitors are placed as close to their respective device pads. Bottom bypass brought out from device. This layout can lead to increased trace length, which will increase the series inductance of the net making it more susceptible to noise and voltage spikes. Figure 60 to Figure 61 show the board layouts.

DAC60096 DAC60096_Bd_Layout-Top_Lyr_SLASEB3.gif Figure 60. DAC60096 Example Board Layout – Top Layer
DAC60096 DAC60096_Bd_Layout-Bott_Lyr_SLASEB3.gif Figure 61. DAC60096 Example Board Layout – Bottom Layer