JAJSSA9 November   2023 DAC61401 , DAC81401

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 5.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 5.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 5.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 5.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 5.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. Register Map
    1. 7.1 Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics

at TA = 25°C, VDD = 5.0 V, IOVDD = 1.8 V, external reference, unipolar ranges: AVSS = 0 V and AVDD ≥ VMAX + 1.5 V for the DAC range, bipolar ranges: AVSS ≤ VMIN − 1.5 V and AVDD ≥ VMAX + 1.5 V for the DAC range, and DAC output unloaded (unless otherwise noted)

GUID-20231018-SS0I-WKRT-KL7Z-MJ8HZRZCKGVZ-low.png
 
Figure 5-4 DAC81401 Relative Accuracy vs Digital Input Code
(Bipolar Outputs)
GUID-20231018-SS0I-SQSH-Z7QF-C6ZBCSKJSXS2-low.png
 
Figure 5-6 DAC81401 DNL vs Digital Input Code
(Bipolar Outputs)
GUID-20231018-SS0I-VJ4V-RFFS-RPR1RCSX1D3L-low.svg
 
Figure 5-8 DAC81401 TUE vs Digital Input Code
(Bipolar Outputs)
GUID-20231018-SS0I-BW35-DSB9-ZD1HLQBZBZT4-low.svg
 
Figure 5-10 DAC61401 Relative Accuracy vs Digital Input Code
(Bipolar Outputs)
GUID-20231018-SS0I-1M6D-BNFT-SQQ3BKQTHV1V-low.svg
 
Figure 5-12 DAC61401 DNL vs Digital Input Code
(Bipolar Outputs)
GUID-20231018-SS0I-KK1Z-T3RP-KRXV0BKWVHS1-low.svg
 
Figure 5-14 DAC61401 TUE vs Digital Input Code
(Bipolar Outputs)
GUID-20231018-SS0I-4LPP-TJHM-ZRNDBTC0KDTQ-low.svg
 
Figure 5-16 DAC81401 Relative Accuracy vs Temperature
GUID-20231018-SS0I-XMKG-RNVG-WHWMN6GGQVQT-low.svg
 
Figure 5-18 DAC61401 Relative Accuracy vs Temperature
GUID-20231018-SS0I-0PJM-CZKN-N3GGRLXGNTWL-low.svg
 
Figure 5-20 TUE vs Temperature
GUID-20231018-SS0I-VD5W-K9GZ-S4KQJPHKKDCM-low.svg
 
Figure 5-22 Unipolar Zero Code Error vs Temperature
GUID-20231018-SS0I-HNHK-N2BZ-W8PVT6DHDFFT-low.svg
 
Figure 5-24 Bipolar Zero Error vs Temperature
GUID-20231018-SS0I-RNM2-CVD3-KXRMBFH9CNLC-low.svg
 
Figure 5-26 Full-Scale Error vs Temperature
GUID-20231018-SS0I-NX9X-QPRZ-9DDNPZDNHTSX-low.svg
 
Figure 5-28 Supply Current (IAVDD, IAVSS)
vs Digital Input Code
GUID-20231018-SS0I-LP6P-MHDL-K51QQGSX6JJK-low.svg
DAC range = ±20 V
Figure 5-30 Supply Current vs Temperature
GUID-20231018-SS0I-MNCX-WGJ3-RPSFJPZC91JQ-low.svg
 
Figure 5-32 Headroom and Footroom From Supply
vs Output Current
GUID-20230925-SS0I-8JJ3-W1WW-JNMMNKPL75G2-low.svg
DAC range = ±10 V
Figure 5-34 Full-Scale Settling Time, Rising Edge
GUID-20230925-SS0I-HPW8-MBDD-4QBSQSGMZ0CF-low.svg
DAC range = ±20 V
Figure 5-36 DAC Output Enable Glitch
GUID-20230925-SS0I-WBKJ-XMWF-GM76MPQGKV33-low.svg
DAC range = ±10 V
Figure 5-38 Glitch Impulse, 1-LSB Step,
Falling Edge
GUID-20231018-SS0I-NCGP-SDL8-0P3LTHZ9XHMQ-low.svg
 
Figure 5-40 Power-Down Response
GUID-20231018-SS0I-RJRD-CRJQ-70VHCBFQCHFW-low.svg
DAC range= 0 V to 5 V midscale code
Figure 5-42 DAC Output Noise
GUID-20231018-SS0I-WJC6-LWTC-QFN1P9Q5F2WL-low.svg
 
Figure 5-44 Internal Reference Voltage
vs Supply Voltage
GUID-20230925-SS0I-1L9D-LWZV-JP7XSXLF39P5-low.svg
 
Figure 5-46 Internal Reference Noise Density vs Frequency
GUID-20231018-SS0I-2CLL-WXXF-SJ1JV1TTSKP8-low.svg
 
 
 
Figure 5-48 Internal Reference Temperature Drift Histogram
GUID-20231018-SS0I-MGHN-MSQG-LGDXVBHXGB8L-low.png
 
Figure 5-5 DAC81401 Relative Accuracy vs Digital Input Code
(Unipolar Outputs)
GUID-20231018-SS0I-ZKXV-WVKP-7DFXRFLVMWFD-low.png
 
Figure 5-7 DAC81401 DNL vs Digital Input Code
(Unipolar Outputs)
GUID-20231018-SS0I-BNP9-LHZK-2SKLNGNTZWRR-low.svg
 
Figure 5-9 DAC81401 TUE vs Digital Input Code
(Unipolar Outputs)
GUID-20231018-SS0I-WNSJ-F6XJ-9X2RG8CZNHSB-low.svg
 
Figure 5-11 DAC61401 Relative Accuracy vs Digital Input Code
(Unipolar Outputs)
GUID-20231018-SS0I-ZJ3D-VRRJ-QC5T8VTKC5MT-low.svg
 
Figure 5-13 DAC61401 DNL vs Digital Input Code
(Unipolar Outputs)
GUID-20231018-SS0I-2M2N-TBQZ-56CVWXNPFLMP-low.svg
 
Figure 5-15 DAC61401 TUE vs Digital Input Code
(Unipolar Outputs)
GUID-20231018-SS0I-PCBZ-SFBB-KLMWKCSQT3WN-low.svg
 
Figure 5-17 DAC81401 DNL vs Temperature
GUID-20231018-SS0I-HMFF-50CM-ZKRBZZBMMJGX-low.svg
 
Figure 5-19 DAC61401 DNL vs Temperature
GUID-20231018-SS0I-T41F-XG0K-CNSHC0NLMNWZ-low.svg
 
Figure 5-21 Unipolar Offset Error vs Temperature
GUID-20231018-SS0I-P8H7-XHNS-7LR7C8D27NXF-low.svg
 
Figure 5-23 Bipolar Zero Code Error vs Temperature
GUID-20231018-SS0I-5KVQ-NH6Q-ZCVKLHCCLH2M-low.svg
 
Figure 5-25 Gain Error vs Temperature
GUID-20231018-SS0I-PPMB-LKR9-LZ2GW052D4FN-low.svg
 
Figure 5-27 Supply Current (IVDD)
vs Digital Input Code
GUID-20231018-SS0I-5LNL-TRCL-LGGFGQ3J0JL8-low.svg
 
Figure 5-29 Supply Current (IIOVDD)
vs Supply Voltage
GUID-20231018-SS0I-WP76-SWRK-6LGBK2X6BV6X-low.svg
DAC range = ±20 V
Figure 5-31 Power-Down Current vs Temperature
GUID-20231018-SS0I-91KS-ML4R-JWCHXJQKVQRV-low.svg
 
Figure 5-33 Source and Sink Capability
GUID-20230925-SS0I-S8RC-KSFB-MLGRHXMLZS2G-low.svg
DAC range = ±10 V
Figure 5-35 Full-Scale Settling Time, Falling Edge
GUID-20230925-SS0I-9J65-KMZJ-BXHPWB8ZQB2C-low.svg
DAC range = ±10 V
Figure 5-37 Glitch Impulse, 1-LSB Step,
Rising Edge
GUID-20231018-SS0I-SSNX-WMNQ-VRSKP5LKQBM2-low.svg
 
Figure 5-39 Power-Up Response
GUID-20230925-SS0I-1PBP-MNJQ-26JCNSG2VPK1-low.svg
DAC range= 0 V to 5 V midscale code
Figure 5-41 DAC Output Noise Density vs Frequency
GUID-20231018-SS0I-XZX5-QBH3-S68S0RQLHLTD-low.svg
 
Figure 5-43 Internal Reference Voltage vs Temperature
GUID-20231031-SS0I-PJKQ-DBDB-KXX1ZWTTGGBZ-low.svg
 
Figure 5-45 Internal Reference Voltage vs Time
GUID-20231018-SS0I-ZQPS-2KMF-JPNZGZC4PJCP-low.svg
 
Figure 5-47 Internal Reference Noise
GUID-20231018-SS0I-3STV-W9ZJ-KWLW2BZFRKLZ-low.svg
VOUT = 0 V (DAC code at midscale), output unloaded,
AVDD = 10 V, AVSS = –10 V, VDD = 5 V,
supply noise VPP = 0.2 V
Figure 5-49 AC Power Supply Rejection Ratio (PSSR-AC)