JAJSE97D June   2017  – May 2019 DAC8740H , DAC8741H

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: DAC8740H
    2.     Pin Functions: DAC8741H
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  HART Modulator
      2. 9.3.2  HART Demodulator
      3. 9.3.3  FOUNDATION Fieldbus or PROFIBUS PA Manchester Encoder
      4. 9.3.4  FOUNDATION Fieldbus or PROFIBUS PA Manchester Decoder
      5. 9.3.5  Internal Reference
      6. 9.3.6  Clock Configuration
      7. 9.3.7  Reset and Power-Down
      8. 9.3.8  Full-Duplex Mode
      9. 9.3.9  I/O Selection
      10. 9.3.10 Jabber Inhibitor
    4. 9.4 Device Functional Modes
      1. 9.4.1 UART Interfaced HART
      2. 9.4.2 UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      3. 9.4.3 SPI Interfaced HART
      4. 9.4.4 SPI Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      5. 9.4.5 Digital Interface
        1. 9.4.5.1 UART
          1. 9.4.5.1.1 UART Carrier Detect
        2. 9.4.5.2 SPI
          1. 9.4.5.2.1 SPI Cyclic Redundancy Check
          2. 9.4.5.2.2 SPI Interrupt Request
    5. 9.5 Register Maps
      1. 9.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 9. CONTROL Register Field Descriptions
      2. 9.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 10. RESET Register Field Descriptions
      3. 9.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 11. MODEM_STATUS Register Field Descriptions
      4. 9.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 12. MODEM_IRQ_MASK Register Field Descriptions
      5. 9.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 13. MODEM_CONTROL Register Field Descriptions
      6. 9.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 14. FIFO_D2M Register Field Descriptions
      7. 9.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 15. FIFO_M2D Register Field Descriptions
      8. 9.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 16. FIFO_LEVEL_SET Register Field Descriptions
      9. 9.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 17. PAFF_JABBER Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Design Recommendations
      2. 10.1.2 Selecting the Crystal or Resonator
      3. 10.1.3 Included Functions and Filter Selection
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 DAC8740H HART Modem
        2. 10.2.2.2 2-Wire Current Loop
        3. 10.2.2.3 Regulator
        4. 10.2.2.4 DAC
        5. 10.2.2.5 Amplifiers
        6. 10.2.2.6 Diodes
        7. 10.2.2.7 Passives
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

all specifications over –40°C to +105°C ambient operating temperature, 2.7 V ≤ AVDD ≤ 5.5 V, 1.71 V ≤ IOVDD ≤ 5.5 V, internal reference, internal filter (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER REQUIREMENTS
AVDD and IOVDD Supply Current (HART Mode)
Demodulator active External clock, –40°C to +85°C 110 150 µA
External clock, –55°C to +105℃ 220 µA
External clock, –40°C to +85°C, external reference 100 140 µA
External clock, –55°C to +105℃, external reference 210 µA
Modulator active External clock, –40°C to +85°C 160 180 µA
External clock, –55°C to +105℃ 250 µA
External clock, –40°C to +85°C, external reference 150 170 µA
External clock, –55°C to +105℃, external reference 240 µA
Crystal oscillator External crystal, 16 pF at XTAL1 and XTAL2 40 65 µA
External crystal, 36 pF at XTAL1 and XTAL2 40 65 µA
Internal oscillator External reference 105 180 µA
SPI interface Additional quiescent current required when interfacing via SPI (DAC8741H only) 5 µA
AVDD and IOVDD Supply Current (FF/PA Mode)
Decoder active External clock, –40°C to +85°C 160 220 µA
External clock, –55°C to +105℃ 330 µA
External clock, –40°C to +85°C, external reference 175 200 µA
External clock, –55°C to +105℃, external reference 320 µA
Encoder active External clock, –40°C to +85°C 175 250 µA
External clock, –55°C to +105℃ 360 µA
External clock, –40°C to +85°C, external reference 165 235 µA
External clock, –55°C to +105℃, external reference 350 µA
Crystal oscillator External crystal, 16 pF at XTAL1 and XTAL2 40 65 µA
External crystal, 36 pF at XTAL1 and XTAL2 40 65 µA
SPI interface Additional quiescent current required when interfacing via SPI (DAC8741H) 5 µA
AVDD and IOVDD Supply Current (All Modes)
Power-down mode Internal reference disabled, –40°C to +85°C, no active clock input 30 60 µA
Internal reference disabled, –55°C to +105℃, no active clock input 182 µA
CLOCK REQUIREMENTS
EXTERNAL CLOCK (HART MODE)
External clock source frequency 3.6864-MHz clock 3.6469 3.6864 3.7232 MHz
1.2288-MHz clock 1.2165 1.2288 1.2411 MHz
EXTERNAL CLOCK (FF/PA MODE)
External clock source frequency 4-MHz clock 3.96 4 4.04 MHz
INTERNAL OSCILLATOR
Frequency –40°C to +105℃ 1.2165 1.2288 1.2411 MHz
VOLTAGE REFERENCE
INTERNAL REFERENCE VOLTAGE
Internal reference voltage 1.47 1.5 1.53 V
Load regulation 1.3 V/mA
Capacitive load Specified by design 1 µF
OPTIONAL EXTERNAL REFERENCE VOLTAGE
External reference input voltage 2.375 2.5 2.625 V
External reference input current Demodulator 4.5 µA
Modulator 4.5 µA
Internal oscillator 4.5 µA
Power-down 4.5 µA
HART MODEM
MOD_IN INPUT (HART MODE)
Input voltage range External reference source, specified by design. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP
Internal reference source, specified by design. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP
Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP
MOD_OUT OUTPUT (HART MODE)
Output voltage AC-coupled (2.2 µF), measured at MOD_OUT pin with 160-Ω load 450 460 480 mVPP
Mark frequency Internal oscillator 1200 Hz
Space frequency Internal oscillator 2200 Hz
Frequency error Internal oscillator, –40°C to +105℃ -1 1 %
Phase continuity error Specified by design 0 Degrees
Minimum resistive load 160-Ω, ac coupled with 2.2 µF, specified by design 160 Ω
Transmit impedance RTS low, measured at the MOD_OUT pin, 1-mA measurement current 13 Ω
RTS high, measured at the MOD_OUT pin, ±200-nA measurement current 250 kΩ
FF / PA MODEM
MOD_IN INPUT (FF/PA MODE)
Input voltage range External reference source, specified by design. Signal applied at the input to the DC blocking capacitor. 0 1 Vp-p
Internal reference enabled, specified by design. Signal applied at the input to the DC blocking capacitor. 0 1 Vp-p
Receiver jitter tolerance Edge-to-edge measurement of Manchester encoded waveforms -3.2 3.2 µs
Receiver sensitivity Threshold for successful carrier detection and decoding, assuming ideal Manchester encoded input trapezoidal signals with 6µs rise time, valid preamble byte(s) and start delimiter byte, using internal filter. 75 mVp-p
MOD_OUT OUTPUT (FF/PA MODE)
Output voltage 800 mVp-p
Maximum amplitude difference Maximum difference in positive and negative amplitude signals -50 50 mV
Transmit bit rate 31.1875 31.25 31.3125 kbit/s
Transmit jitter Measured with respect to ideal crossing of high time and low time -0.8 0.8 µs
Output signal distortion Measured peak to trough distortion for positive and negative amplitude voltage outputs -10 10 %
Rise and fall time 10% to 90% of peak to peak signal 8 µs
Slew rate 10% to 90% of peak to peak signal 0.2 V/µs
DIGITAL REQUIREMENTS
DIGITAL INPUTS
VIH, input high voltage 0.7 x IOVDD V
VIL, input low voltage 0.3 x IOVDD V
CLK_CFG0, input high voltage Specified by design 0.8 x IOVDD V
CLK_CFG0, input mid-scale voltage Specified by design 0.4 x IOVDD 0.55 x IOVDD V
CLK_CFG0, input low voltage Specified by design 0.15 x IOVDD
Input current -1 1 µA
Input capcitance 5 pF
DIGITAL OUTPUTS
VOH, output high voltage 200-µA source or sink IOVDD - 0.5 V
VOL, output low voltage 200-µA source or sink 0.4 V