JAJSPX6A データシート

JAJSPX6A August 2017 – February 2023 DLP650NE

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

FYE|350

サーマルパッド・メカニカル・データ

発注情報

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted). Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

		MIN	MAX	UNIT
SUPPLY VOLTAGES
VCC	Supply voltage for LVCMOS core logic⁽¹⁾	–0.5	4	V
VCCI	Supply voltage for LVDS receivers⁽¹⁾	–0.5	4	V
VOFFSET	Supply voltage for HVCMOS and micromirror electrode⁽¹⁾⁽²⁾	–0.5	9	V
VBIAS	Supply voltage for micromirror electrode⁽¹⁾	–0.5	17	V
VRESET	Supply voltage for micromirror electrode⁽¹⁾	–11	0.5	V
\| VCC – VCCI \|	Supply voltage change (absolute value)⁽³⁾		0.3	V
\| VBIAS – VOFFSET \|	Supply voltage change (absolute value)⁽⁴⁾		8.75	V
INPUT VOLTAGES
	Input voltage for all other LVCMOS input pins⁽¹⁾	–0.5	VCC + 0.15	V
	Input voltage for all other LVDS input pins⁽¹⁾⁽⁵⁾	–0.5	VCCI + 0.15	V
\| V_ID \|	Input differential voltage (absolute value)⁽⁶⁾		700	mV
I_ID	Input differential current⁽⁶⁾		7	mA
CLOCKS
ƒ_clock	Clock frequency for LVDS interface, DCLK (all channels)		460	MHz
ENVIRONMENTAL
T_ARRAY and T_WINDOW	Temperature, operating⁽⁷⁾	0	90	°C
T_ARRAY and T_WINDOW	Temperature: non-operating⁽⁷⁾	–40	90	°C
\|T_DELTA\|	Absolute Temperature delta between any point on the window edge and the ceramic test point TP1⁽⁸⁾		30	°C
T_DP	Dew Point temperature, operating and non-operating (non-condensing)		81	°C

(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) VOFFSET supply transients must fall within specified voltages.

(3) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.

(4) To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit. Refer to Section 8 for additional information.

(5) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(6) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors

(7) The highest temperature of the active array (as calculated by Section 7.6) or of any point along the Window Edge as defined in Figure 7-1. The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, add a test point to that location.

(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to result in the worst-case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.