JAJSGN4F August   2012  – February 2019 DLPC410

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Binary Pattern Data Path
        1. 8.3.1.1  DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses
        2. 8.3.1.2  DCLKIN Input Clocks
        3. 8.3.1.3  DVALID Input Signals
        4. 8.3.1.4  DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses
        5. 8.3.1.5  DCLKOUT Output Clocks
        6. 8.3.1.6  SCTRL Output Signals
        7. 8.3.1.7  Supported DMD Bus Sizes
        8. 8.3.1.8  Row Cycle definition
        9. 8.3.1.9  DLP9500 and DLP9500UV Input Data Formatting
        10. 8.3.1.10 DLP7000 and DLP7000UV Input Data Bus
        11. 8.3.1.11 DLP650LNIR Input Data Bus
      2. 8.3.2 Data Bus Operations
        1. 8.3.2.1 Row Addressing
        2. 8.3.2.2 Single Row Write Operation
        3. 8.3.2.3 No-Op Row Cycle Description
      3. 8.3.3 DMD Block Operations
        1. 8.3.3.1 Mirror Clocking Pulse (MCP)
        2. 8.3.3.2 Reset Active (RST_ACTIVE)
        3. 8.3.3.3 DMD Block Control Signals
          1. 8.3.3.3.1 Block Mode - BLK_MD1:0)
          2. 8.3.3.3.2 Block Address - BLK_AD(3:0)
          3. 8.3.3.3.3 Reset 2 Blocks - RST2BLK
        4. 8.3.3.4 DMD Block Operations
          1. 8.3.3.4.1 Global Reset (MCP) Consideration
      4. 8.3.4 Other Data Control Inputs
        1. 8.3.4.1 Complement Data
        2. 8.3.4.2 North/South Flip
      5. 8.3.5 Miscellaneous Control Inputs
        1. 8.3.5.1 ARST
        2. 8.3.5.2 CLKIN_R
        3. 8.3.5.3 DMD_A_RESET
        4. 8.3.5.4 Watchdog Timer Enable (WDT_ENABLE)
      6. 8.3.6 Miscellaneous Status Outputs
        1. 8.3.6.1 INIT_ACTIVE
        2. 8.3.6.2 DMD_Type(3:0)
        3. 8.3.6.3 DDC_VERSION(3:0)
        4. 8.3.6.4 LED0
        5. 8.3.6.5 LED1
        6. 8.3.6.6 DLPA200 Control Signals
        7. 8.3.6.7 ECM2M_TP_ (31:0)
    4. 8.4 Device Functional Modes
      1. 8.4.1 DLPC410 Initialization and Training
        1. 8.4.1.1 Initialization
        2. 8.4.1.2 input Data Interface (DIN) Training Pattern
      2. 8.4.2 DLPC410 Operational Modes
        1. 8.4.2.1 Single Block Mode
        2. 8.4.2.2 Single Block Phased Mode
        3. 8.4.2.3 Dual Block Mode
        4. 8.4.2.4 Quad Block Mode
        5. 8.4.2.5 Global Mode
        6. 8.4.2.6 DMD Park Mode
        7. 8.4.2.7 DMD Idle Mode
      3. 8.4.3 LOAD4 Functionality (enabled with DLPR410A)
        1. 8.4.3.1 Enabling LOAD4
        2. 8.4.3.2 Loading Data with LOAD4
        3. 8.4.3.3 Row Mapping with LOAD4
        4. 8.4.3.4 Using Block Clear with LOAD4
        5. 8.4.3.5 Timing Requirements for LOAD4
        6. 8.4.3.6 Global Binary Pattern Rate increases using LOAD4
        7. 8.4.3.7 Special LOAD4 considerations
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Description
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Debugging Guidelines
      2. 9.3.2 Initialization
        1. 9.3.2.1 Calibration
        2. 9.3.2.2 DLPA200 Number 1 Initialization
        3. 9.3.2.3 DMD Initialization
          1. 9.3.2.3.1 DMD Device ID Check
          2. 9.3.2.3.2 DMD Device OK
        4. 9.3.2.4 DLPA200 Number 2 Initialization
        5. 9.3.2.5 Command Sequence Initialization
      3. 9.3.3 Image Display Issues
        1. 9.3.3.1 Present Data to DLPC410
        2. 9.3.3.2 Load Data to DMD
        3. 9.3.3.3 Mirror Clocking Pulse
  10. 10Power Supply Recommendations
    1. 10.1 Power Down Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLPC410 DMD Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
    3. 11.3 DLPC410 Chipset Connections
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイス・マーキング
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DLP|676
サーマルパッド・メカニカル・データ
発注情報

4 改訂履歴

Changes from E Revision (January 2019) to F Revision

  • Modified functions for TP4-TP31 Go
  • Corrected DLP650LNIR Bus A Pixel Mapping Go
  • Corrected DLP650LNIR Bus B Pixel Mapping Go
  • Removed ECP2M calibration feedback pins Go
  • Removed ECP2M DLPA200 Init Status pin Go
  • Removed ECP2M DMD Init Status pin Go
  • Adjusted pinouts of DMD OK Status bits Go
  • Removed the ECP2_M TP20 referring to AA18 instead Go

Changes from D Revision (December 2018) to E Revision

  • Changed ARST description that was incorrectly described in DLPS024 Revision D.Go

Changes from C Revision (December 2015) to D Revision

  • サポートされる DMD (複数) に新しい DLP650LNIR を追加Go
  • 入力データ・クロック速度を 400MHz のみに変更Go
  • 最新の市場に合わせて「アプリケーション」一覧を更新Go
  • 概略回路図を変更し、新しい DLP650LNIR を追加Go
  • Changed pin DDC_SPARE_0 to LOAD4Go
  • Removed 200MHz - new revision tested at 400MHz only Go
  • Re-organization of Detailed Description for flow, clarity, and readabilityGo
  • Added DLP650LNIR functional block diagram Go
  • Updated DLP7000 functional block diagram (no technical changes)Go
  • Updated DLP9500 functional block diagram (no technical changes)Go
  • Added new DLP650LNIR DMD Characteristics to Table 2Go
  • Added DLP650LNIR DMD to Row Addressing and Table 11Go
  • Re-worded the Block Operations section for clarity. Go
  • Added new DLP650LNIR DMD CharacteristicsGo
  • Added/edited LOAD4 sections, enabled by DLPR410AGo
  • Removed reference to 200 MHz input data clock.Go
  • Added the DLP650LNIR and its block load time to Table 16Go
  • Added Table 17Go
  • Combined Application Example Diagrams to encompass all DLPC410 supported DMDs Go
  • Added DLP650LNIR to Detailed Design procedure section Go
  • Added Figure 25 - DLP650LNIR window transmittance Go
  • Changed "Generate Data" to "Present Data to DLPC410" Go
  • Changed "DLPC410 DMD data signals" to "LVDS data bus differential pairs"Go
  • TI 型番 2510440-001 への参照を削除Go
  • Discovery チップセットのデータシートを削除、DLP650LNIR のデータシートを追加、他のデバイス名を訂正Go

Changes from B Revision (June 2013) to C Revision

  • Added 「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションGo
  • ドキュメント全体を通して Discovery 4100 への参照を削除し、DLPR4101 を削除Go
  • Added 「特長」と「概要」に DLP7000UV と DLP9500UV をGo
  • Added note - Xlilinx System Monitor analog supply & ground - "must be connected to ground" (AVDD_0 & AVSS_0)Go
  • Changed "DAD A" descriptions to "DLPA200 number 1" and "DAD B" descriptions to "DLPA200 number 2"Go
  • Reversed DDC_Bnn_VR pairs pullups / pulldowns (for nn =12, 15, and 16))Go
  • Changed Pin # C22 name from DDC_B11_VRP (duplicate) to DDC_B15_VRP Go
  • Added "Not used" to description for DMD_B_RESET and DMD_B_SCPENGo
  • Added TP14 and TP17 note - Xilinx Temperature Diode Go
  • Added "in Reference Design" to ECP2 Mictor pin notesGo
  • Changed ECP2 pin description from "Not Defined" to "Not Used" Go
  • Added ECP2_M_TP[3:29] descriptions and active stateGo
  • Deleted duplicate pin numbers M13 and M14 Go
  • Changed Description from "DMD Power" to "DMD Power Good indicator" Go
  • Changed duplicate pin name from RSVD_0 to RSVD_1Go
  • Updated pin description for SCPDI and SCPDO Go
  • Changed STEPVCC to connect to ground, active "Hi" to "-", and clock to "-" Go
  • Changed Description from "JTAG Data Clock" to "JTAG Data" Go
  • Changed pin names for VCCO_n_n pins to list each pin separatelyGo
  • Added note about Xilinx System Monitor differential pins (VN_0 & VP_0) and reference voltage (VREFN_0 & VREFP_0)Go
  • Changed Description from "DMD Reset Watchdog" to "DMD Mirror Clocking Pulse Watchdog" Go
  • Deleted duplicate pin numbers in "UNUSED" pin listGo
  • Updated the functional block diagramsGo
  • Moved DLP7000 / DLP7000UV and DLP9500 / DLP9500UV Example Block Diagrams from Functional Block Diagram section to Typical Application Section Go
  • Deleted the "Step DMD SRAM Memory Voltage" and "Load 4" Enhanced Functionality (with DLPR4101 PROM only)" sectionsGo
  • Updated the embedded example block diagramsGo
  • Added DLP7000UV and DLP9500UV well suited for direct imaging lithography, 3D printing, and UV applications Go
  • Added Debugging Guidelines sectionGo
  • Changed maximum differential trace length from 100 to 150 matching Table 13.Go
  • Added DLP7000UV および DLP9500UV 関連のドキュメントをGo

Changes from A Revision (September 2012) to B Revision

  • Changed 「特長」の「最高 32kHz の 1 ビット・バイナリ・パターン速度」を「最高 32kHz の 1 ビット・バイナリ・パターン速度 (DLPR4101 とともに使用した場合は最高 48kHz)」にGo
  • Added Section "Load 4" Enhanced Functionality (with DLPR4101 PROM only)Go
  • Added DLPR410 に DLPR4101 をGo

Changes from * Revision (August 2012) to A Revision