JAJSFL2H March 2016 – November 2019 DRA722 , DRA724 , DRA725 , DRA726
PRODUCTION DATA.
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The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories.
General SPI features:
NOTE
For more information, see Quad Serial Peripheral Interface section in the device TRM.
CAUTION
The I/O Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode 3).
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.
Table 7-45 and Table 7-46 Present Timing and Switching Characteristics for Quad SPI Interface.
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
Q1 | tc(SCLK) | Cycle time, sclk | Default Timing Mode, Clock Mode 0 | 11.71 | ns | |
Default Timing Mode, Clock Mode 3 | 20.8 | ns | ||||
Q2 | tw(SCLKL) | Pulse duration, sclk low | Y × P - 1 (1) | ns | ||
Q3 | tw(SCLKH) | Pulse duration, sclk high | Y × P - 1 (1) | ns | ||
Q4 | td(CS-SCLK) | Delay time, sclk falling edge to cs active edge, CS3:0 | Default Timing Mode | -M × P - 1.6 (2)(3) | -M × P + 2.6 (2)(3) | ns |
Q5 | td(SCLK-CS) | Delay time, sclk falling edge to cs inactive edge, CS3:0 | Default Timing Mode | N × P - 1.6 (2)(3) | N × P + 2.6 (2)(3) | ns |
Q6 | td(SCLK-D0) | Delay time, sclk falling edge to d[0] transition | Default Timing Mode | -1.6 | 2.6 | ns |
Q7 | tena(CS-D0LZ) | Enable time, cs active edge to d[0] driven (lo-z) | -P - 3.5 | -P + 2.5 | ns | |
Q8 | tdis(CS-D0Z) | Disable time, cs active edge to d[0] tri-stated (hi-z) | -P - 2.5 | -P + 2.0 | ns | |
Q9 | td(SCLK-D0) | Delay time, sclk first falling edge to first d[0] transition | PHA=0 Only, Default Timing Mode | -1.6 - P(2) | 2.6 - P(2) | ns |
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
Q12 | tsu(D-RTCLK) | Setup time, d[3:0] valid before falling rtclk edge | Default Timing Mode, Clock Mode 0 | 4.6 | ns | |
tsu(D-SCLK) | Setup time, d[3:0] valid before falling sclk edge | Default Timing Mode, Clock Mode 3 | 12.3 | ns | ||
Q13 | th(RTCLK-D) | Hold time, d[3:0] valid after falling rtclk edge | Default Timing Mode, Clock Mode 0 | -0.1 | ns | |
th(SCLK-D) | Hold time, d[3:0] valid after falling sclk edge | Default Timing Mode, Clock Mode 3 | 0.1 | ns | ||
Q14 | tsu(D-SCLK) | Setup time, final d[3:0] bit valid before final falling sclk edge | Default Timing Mode, Clock Mode 3 | 12.3 - P (1) | ns | |
Q15 | th(SCLK-D) | Hold time, final d[3:0] bit valid after final falling sclk edge | Default Timing Mode, Clock Mode 3 | 0.1 + P (1) | ns |
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information see Control Module chapter in the device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for QSPI. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-47Manual Functions Mapping for QSPI for a definition of the Manual modes.
Table 7-47 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | QSPI1_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 1 | |||
T7 | gpmc_a3 | 0 | 0 | CFG_GPMC_A3_OUT | qspi1_cs2 |
P6 | gpmc_a4 | 0 | 0 | CFG_GPMC_A4_OUT | qspi1_cs3 |
R3 | gpmc_a13 | 0 | 0 | CFG_GPMC_A13_IN | qspi1_rtclk |
T2 | gpmc_a14 | 2247 | 1186 | CFG_GPMC_A14_IN | qspi1_d3 |
U2 | gpmc_a15 | 2176 | 1197 | CFG_GPMC_A15_IN | qspi1_d2 |
U1 | gpmc_a16 | 2229 | 1268 | CFG_GPMC_A16_IN | qspi1_d0 |
U1 | gpmc_a16 | 0 | 0 | CFG_GPMC_A16_OUT | qspi1_d0 |
P3 | gpmc_a17 | 2251 | 1217 | CFG_GPMC_A17_IN | qspi1_d1 |
R2 | gpmc_a18 | 0 | 0 | CFG_GPMC_A18_OUT | qspi1_sclk |
P2 | gpmc_cs2 | 0 | 0 | CFG_GPMC_CS2_OUT | qspi1_cs0 |
P1 | gpmc_cs3 | 0 | 0 | CFG_GPMC_CS3_OUT | qspi1_cs1 |