JAJSFL2H March 2016 – November 2019 DRA722 , DRA724 , DRA725 , DRA726
PRODUCTION DATA.
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NOTE
For more information, see Memory Subsystem chapter, General-Purpose Memory Controller section in the device TRM.
SIGNAL NAME | DESCRIPTION | TYPE | BALL |
---|---|---|---|
gpmc_ad0 | GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1 in A/D multiplexed mode | IO | M6 |
gpmc_ad1 | GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2 in A/D multiplexed mode | IO | M2 |
gpmc_ad2 | GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3 in A/D multiplexed mode | IO | L5 |
gpmc_ad3 | GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4 in A/D multiplexed mode | IO | M1 |
gpmc_ad4 | GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5 in A/D multiplexed mode | IO | L6 |
gpmc_ad5 | GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6 in A/D multiplexed mode | IO | L4 |
gpmc_ad6 | GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7 in A/D multiplexed mode | IO | L3 |
gpmc_ad7 | GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8 in A/D multiplexed mode | IO | L2 |
gpmc_ad8 | GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9 in A/D multiplexed mode | IO | L1 |
gpmc_ad9 | GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10 in A/D multiplexed mode | IO | K2 |
gpmc_ad10 | GPMC Data 10 in A/D nonmultiplexed mode and additionally Address 11 in A/D multiplexed mode | IO | J1 |
gpmc_ad11 | GPMC Data 11 in A/D nonmultiplexed mode and additionally Address 12 in A/D multiplexed mode | IO | J2 |
gpmc_ad12 | GPMC Data 12 in A/D nonmultiplexed mode and additionally Address 13 in A/D multiplexed mode | IO | H1 |
gpmc_ad13 | GPMC Data 13 in A/D nonmultiplexed mode and additionally Address 14 in A/D multiplexed mode | IO | J3 |
gpmc_ad14 | GPMC Data 14 in A/D nonmultiplexed mode and additionally Address 15 in A/D multiplexed mode | IO | H2 |
gpmc_ad15 | GPMC Data 15 in A/D nonmultiplexed mode and additionally Address 16 in A/D multiplexed mode | IO | H3 |
gpmc_a0 | GPMC Address 0. Only used to effectively address 8-bit data nonmultiplexed memories | O | R6 / P4 |
gpmc_a1 | GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D multiplexed mode | O | T9 / P1 |
gpmc_a2 | GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D multiplexed mode | O | T6 / N1 |
gpmc_a3 | GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D multiplexed mode | O | T7 / M4 |
gpmc_a4 | GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D multiplexed mode | O | P6 |
gpmc_a5 | GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D multiplexed mode | O | R9 |
gpmc_a6 | GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D multiplexed mode | O | R5 |
gpmc_a7 | GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D multiplexed mode | O | P5 |
gpmc_a8 | GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D multiplexed mode | O | N7 |
gpmc_a9 | GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D multiplexed mode | O | R4 |
gpmc_a10 | GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D multiplexed mode | O | N9 |
gpmc_a11 | GPMC address 11 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | P9 |
gpmc_a12 | GPMC address 12 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | P4 |
gpmc_a13 | GPMC address 13 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | R3 / K7 / P2 |
gpmc_a14 | GPMC address 14 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | T2 / M7 / P1 |
gpmc_a15 | GPMC address 15 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | U2 / J5 / N2 |
gpmc_a16 | GPMC address 16 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | U1 / K6 / R6 |
gpmc_a17 | GPMC address 17 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | P3 / J7 / E1 |
gpmc_a18 | GPMC address 18 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | R2 / J4 / H7 |
gpmc_a19 | GPMC address 19 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | K7(3) / J6 |
gpmc_a20 | GPMC address 20 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | M7(3) / H4 |
gpmc_a21 | GPMC address 21 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | J5(3) / H5 |
gpmc_a22 | GPMC address 22 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | K6(3) / H6 |
gpmc_a23 | GPMC address 23 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | F6 / J7 / N1 / P2 |
gpmc_a24 | GPMC address 24 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | D3 / J4(3) / P1 |
gpmc_a25 | GPMC address 25 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | E6 / J6(3) / N2 |
gpmc_a26 | GPMC address 26 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | F5 / H4(3) / R6 |
gpmc_a27 | GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D multiplexed mode | O | G1 / H5(3) / E1 / H7 |
gpmc_cs0 | GPMC Chip Select 0 (active low) | O | T1 |
gpmc_cs1 | GPMC Chip Select 1 (active low) | O | H6 |
gpmc_cs2 | GPMC Chip Select 2 (active low) | O | P2 |
gpmc_cs3 | GPMC Chip Select 3 (active low) | O | P1 |
gpmc_cs4 | GPMC Chip Select 4 (active low) | O | N6 |
gpmc_cs5 | GPMC Chip Select 5 (active low) | O | M4 |
gpmc_cs6 | GPMC Chip Select 6 (active low) | O | N1 |
gpmc_cs7 | GPMC Chip Select 7 (active low) | O | P7 |
gpmc_clk(1)(2) | GPMC Clock output | IO | P7 |
gpmc_advn_ale | GPMC address valid active low or address latch enable | O | N1 |
gpmc_oen_ren | GPMC output enable active low or read enable | O | M5 |
gpmc_wen | GPMC write enable active low | O | M3 |
gpmc_ben0 | GPMC lower-byte enable active low | O | N6 |
gpmc_ben1 | GPMC upper-byte enable active low | O | M4 |
gpmc_wait0 | GPMC external indication of wait 0 | I | N2 |
gpmc_wait1 | GPMC external indication of wait 1 | I | P7 / N1 |