JAJSII9E april   2020  – june 2023 DRA821U , DRA821U-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
    1. 3.1 機能ブロック図
  5. Revision History
  6. Device Comparison
    1. 5.1 Related Products
  7. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
        2. 6.3.2.2 DDRSS Mapping
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
        2. 6.3.9.2 MAIN Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW5G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MAIN Domain
        2. 6.3.21.2 MCU Domain
      22. 6.3.22 MCASP
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 DMTIMER
        1. 6.3.23.1 MAIN Domain
        2. 6.3.23.2 MCU Domain
      24. 6.3.24 Emulation and Debug
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 System and Miscellaneous
        1. 6.3.25.1 Boot Mode Configuration
          1. 6.3.25.1.1 MAIN Domain
          2. 6.3.25.1.2 MCU Domain
        2. 6.3.25.2 Clock
          1. 6.3.25.2.1 MAIN Domain
          2. 6.3.25.2.2 WKUP Domain
        3. 6.3.25.3 System
          1. 6.3.25.3.1 MAIN Domain
          2. 6.3.25.3.2 WKUP Domain
          3. 6.3.25.3.3 VMON
        4. 6.3.25.4 EFUSE
      26. 6.3.26 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Power-On-Hours (POH)
    5. 7.5 Operating Performance Points
    6. 7.6 Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  ADC12BT Electrical Characteristics
      7. 7.6.7  LVCMOS Electrical Characteristics
      8. 7.6.8  USB2PHY Electrical Characteristics
      9. 7.6.9  SERDES Electrical Characteristics
      10. 7.6.10 DDR Electrical Characteristics
    7. 7.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8 Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameters and Information
      2. 7.9.2 Power Supply Sequencing
        1. 7.9.2.1 Power Supply Slew Rate Requirement
        2. 7.9.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.9.2.4 Independent MCU and Main Domains Power- Up Sequencing
        5. 7.9.2.5 Independent MCU and Main Domains Power- Down Sequencing
        6. 7.9.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.9.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.9.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.9.3 System Timing
        1. 7.9.3.1 Reset Timing
        2. 7.9.3.2 Safety Signal Timing
        3. 7.9.3.3 Clock Timing
      4. 7.9.4 Clock Specifications
        1. 7.9.4.1 Input Clocks / Oscillators
          1. 7.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.9.4.1.1.1 Load Capacitance
            2. 7.9.4.1.1.2 Shunt Capacitance
          2. 7.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.9.4.1.3.1 Load Capacitance
            2. 7.9.4.1.3.2 Shunt Capacitance
          4. 7.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.9.4.1.5 Auxiliary OSC1 Not Used
          6. 7.9.4.1.6 WKUP_LF_CLKIN Internal Oscillator Clock Source
          7. 7.9.4.1.7 WKUP_LF_CLKIN Not Used
        2. 7.9.4.2 Output Clocks
        3. 7.9.4.3 PLLs
        4. 7.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 7.9.4.5 Interface Clock Specifications
          1. 7.9.4.5.1 Interface Clock Terminology
          2. 7.9.4.5.2 Interface Clock Frequency
      5. 7.9.5 Peripherals
        1. 7.9.5.1  ATL
          1. 7.9.5.1.1 ATL_PCLK Timing Requirements
          2. 7.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.9.5.2  CPSW2G
          1. 7.9.5.2.1 CPSW2G RMII Timings
            1. 7.9.5.2.1.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.9.5.2.1.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.9.5.2.1.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          2. 7.9.5.2.2 CPSW2G RGMII Timings
            1. 7.9.5.2.2.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.9.5.2.2.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.9.5.2.2.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.9.5.2.2.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        3. 7.9.5.3  CPSW5G
          1. 7.9.5.3.1 CPSW5G MDIO Interface Timings
          2. 7.9.5.3.2 CPSW5G RMII Timings
            1. 7.9.5.3.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.9.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.9.5.3.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 7.9.5.3.3 CPSW5G RGMII Timings
            1. 7.9.5.3.3.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.9.5.3.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.9.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.9.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        4. 7.9.5.4  DDRSS
        5. 7.9.5.5  ECAP
          1. 7.9.5.5.1 Timing Requirements for ECAP
          2. 7.9.5.5.2 Switching Characteristics for ECAP
        6. 7.9.5.6  EPWM
          1. 7.9.5.6.1 Timing Requirements for EPWM
          2. 7.9.5.6.2 Switching Characteristics for EPWM
        7. 7.9.5.7  EQEP
          1. 7.9.5.7.1 Timing Requirements for EQEP
          2. 7.9.5.7.2 Switching Characteristics for EQEP
        8. 7.9.5.8  GPIO
        9. 7.9.5.9  GPMC
          1. 7.9.5.9.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.9.5.9.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.9.5.9.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.9.5.9.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.9.5.9.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.9.5.9.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.9.5.9.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.9.5.9.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.9.5.9.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        10. 7.9.5.10 HyperBus
          1. 7.9.5.10.1 Timing Requirements for HyperBus Initialization
          2. 7.9.5.10.2 HyperBus 166 MHz Switching Characteristics
          3. 7.9.5.10.3 HyperBus 100 MHz Switching Characteristics
        11. 7.9.5.11 I2C
        12. 7.9.5.12 I3C
        13. 7.9.5.13 MCAN
        14. 7.9.5.14 MCASP
          1. 7.9.5.14.1 Timing Requirements for MCASP
        15. 7.9.5.15 MCSPI
          1. 7.9.5.15.1 MCSPI — Controller Mode
          2. 7.9.5.15.2 MCSPI — Peripheral Mode
        16. 7.9.5.16 eMMC/SD/SDIO
          1. 7.9.5.16.1 MMCSD0 - eMMC Interface
            1. 7.9.5.16.1.1 Legacy SDR Mode
            2. 7.9.5.16.1.2 High Speed SDR Mode
            3. 7.9.5.16.1.3 High Speed DDR Mode
            4. 7.9.5.16.1.4 HS200 Mode
            5. 7.9.5.16.1.5 HS400 Mode
          2. 7.9.5.16.2 MMCSDi — MMCSD1 — SD/SDIO Interface
            1. 7.9.5.16.2.1 Default speed Mode
            2. 7.9.5.16.2.2 High Speed Mode
            3. 7.9.5.16.2.3 UHS–I SDR12 Mode
            4. 7.9.5.16.2.4 UHS–I SDR25 Mode
            5. 7.9.5.16.2.5 UHS–I SDR50 Mode
            6. 7.9.5.16.2.6 UHS–I DDR50 Mode
            7. 7.9.5.16.2.7 UHS–I SDR104 Mode
        17. 7.9.5.17 NAVSS
          1. 7.9.5.17.1 Timing Requirements for CPTS Input
          2. 7.9.5.17.2 Switching Characteristics for CPTS Output
        18. 7.9.5.18 OSPI
          1. 7.9.5.18.1 OSPI With Data Training
            1. 7.9.5.18.1.1 OSPI Switching Characteristics – Data Training
          2. 7.9.5.18.2 OSPI Without Data Training
            1. 7.9.5.18.2.1 OSPI Switching Characteristics – DDR Mode
            2. 7.9.5.18.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.9.5.18.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.9.5.18.2.4 OSPI Timing Requirements – SDR Mode
        19. 7.9.5.19 PCIE
        20. 7.9.5.20 Timers
          1. 7.9.5.20.1 Timing Requirements for Timers
          2. 7.9.5.20.2 Switching Characteristics for Timers
        21. 7.9.5.21 UART
          1. 7.9.5.21.1 UART Timing Requirements
          2. 7.9.5.21.2 UART Switching Characteristics
        22. 7.9.5.22 USB
      6. 7.9.6 Emulation and Debug
        1. 7.9.6.1 Debug Trace
        2. 7.9.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
          1. 7.9.6.2.1 JTAG Electrical Data and Timing
            1. 7.9.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG
            2. 7.9.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
    3. 8.3 Other Subsystems
      1. 8.3.1 MSMC
      2. 8.3.2 NAVSS
        1. 8.3.2.1 NAVSS0
        2. 8.3.2.2 MCU_NAVSS
      3. 8.3.3 PDMA Controller
      4. 8.3.4 Peripherals
        1. 8.3.4.1  ADC
        2. 8.3.4.2  ATL
        3. 8.3.4.3  CPSW2G
        4. 8.3.4.4  CPSW5G
        5. 8.3.4.5  DCC
        6. 8.3.4.6  DDRSS
        7. 8.3.4.7  ECAP
        8. 8.3.4.8  EPWM
        9. 8.3.4.9  ELM
        10. 8.3.4.10 ESM
        11. 8.3.4.11 EQEP
        12. 8.3.4.12 GPIO
        13. 8.3.4.13 GPMC
        14. 8.3.4.14 Hyperbus
        15. 8.3.4.15 I2C
        16. 8.3.4.16 I3C
        17. 8.3.4.17 MCAN
        18. 8.3.4.18 MCASP
        19. 8.3.4.19 MCRC Controller
        20. 8.3.4.20 MCSPI
        21. 8.3.4.21 MMC/SD
        22. 8.3.4.22 OSPI
        23. 8.3.4.23 PCIE
        24. 8.3.4.24 SerDes
        25. 8.3.4.25 WWDT
        26. 8.3.4.26 Timers
        27. 8.3.4.27 UART
        28. 8.3.4.28 USB
  10. Applications, Implementation, and Layout
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 USB VBUS Design Guidelines
      4. 9.3.4 System Power Supply Monitor Design Guidelines
      5. 9.3.5 High Speed Differential Signal Routing Guidance
      6. 9.3.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ALM|433
サーマルパッド・メカニカル・データ
発注情報

Reset Timing

Tables and figures provided in this section define timing requirements and switching characteristics for reset related signals.

Table 7-6 MCU_PORz Timing Requirements see Figure 7-10
NO.   MIN TYP MAX UNIT
RST1 th(MCUD_SUPPLIES_VALID - MCU_PORz) Hold time, MCU_PORz active (low) at Power-up after all MCU DOMAIN supplies valid (using external crystal) N + 1200(2) 9500000 ns
RST2 Hold time, MCU_PORz active (low) at Power-up after all MCU DOMAIN supplies(1) valid and external clock stable (using external LVCMOS oscillator) 1200 ns
RST3 tw(MCU_PORzL) Pulse Width minimum, MCU_PORz low after Power-up (without removal of Power or system reference clock MCU_OSC0_XI/XO) 1200 ns
For definition of the MCU DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence TBD.
N = oscillator start-up time
GUID-77930A33-A07B-4F99-8808-A71D081AEE88-low.gif Figure 7-10 MCU_PORz Timing Requirements
Table 7-7 PORz Timing Requirements see Figure 7-11
NO. MIN MAX UNIT
RST4 th(MAIND_SUPPLIES_VALID - PORz) Hold time, PORz active (low) at Power-up after all MAIN DOMAIN supplies1 valid 1200 ns
RST5 tw(PORzL) Pulse Width minimum, PORz low after Power-up 1200 ns
  1. For definition of the MAIN DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence TBD.
GUID-C05A8B7F-96D5-49D5-A091-C19C9BFDA911-low.gif Figure 7-11 PORz Timing Requirements
Table 7-8 MCU_PORz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 7-12
NO. PARAMETER MODE MIN MAX UNIT
RST10 td(MCU_PORzL-MCU_RESETSTATzL) Delay time, MCU_PORz active (low) to MCU_RESETSTATz active (low) 0 ns
RST11 td(MCU_PORzH-MCU_RESETSTATzH) Delay time, MCU_PORz inactive (high) to MCU_RESETSTATz inactive (high) POST
bypass
12000*S(1) ns
RST12 td(MCU_PORzL-RESETSTATzL) Delay time, MCU_PORz active (low) to RESETSTATz active (low) 0 ns
RST13 td(MCU_PORzH-RESETSTATzH) Delay time, MCU_PORz inactive (high) to RESETSTATz inactive (high) 14500*S(1) ns
RST16 tw(MCU_RESETSTATzL) Pulse Width Minimum MCU_RESETSTATz low 3900*S(1) ns
RST17 tw(RESETSTATzL) Pulse Width Minimum RESETSTATz low 2650*S(1) ns
S = MCU_OSC0_XI/XO clock period.
GUID-20221014-SS0I-FFS0-SLTX-WRDSRSH0HN23-low.gif Figure 7-12 MCU_PORz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics
Table 7-9 PORz Initiates; PORz_OUT and RESETSTATz Switching Characteristics see Figure 7-13
NO. PARAMETER MODE MIN MAX UNIT
RST20 td(PORzL-RESETSTATzL) Delay time, PORz active (low) to RESETSTATz active (low) T(1)  
CTRLMMR_WKUP_POR_RST
_CTRL[0].POR_RST_ISO_
DONE_Z = 0
0 ns
RST21 td(PORzH-RESETSTATzH) Delay time, PORz active (high) to RESETSTATz active (high) 14500*S(2)   ns
T = Reset Isolation Time (Software Dependent).
S = MCU_OSC0_XI/XO clock period.
GUID-20221014-SS0I-VSXB-6LR3-ZNG1WB21BNPM-low.gif Figure 7-13 PORz initiates; RESETSTATz Switching Characteristics
Table 7-10 MCU_RESETz Timing Requirements see Figure 7-14
NO. MIN MAX UNIT
RST22 tw(MCU_RESETzL)(1) Pulse Width minimum, MCU_RESETz active (low) 1200 ns
Timing for MCU_RESETz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-11 MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 7-14
NO. PARAMETER MIN MAX UNIT
RST23 td(MCU_RESETzL-MCU_RESETSTATzL) Delay time, MCU_RESETz active (low) to MCU_RESETSTATz active (low) 800   ns
RST24 td(MCU_RESETzH-MCU_RESETSTATzH) Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz inactive (high) 3900*S(1)   ns
RST25 td(MCU_RESETzL-RESETSTATzL) Delay time, MCU_RESETz active (low) to RESETSTATz active (low) 800   ns
RST26 td(MCU_RESETzH-RESETSTATzH) Delay time, MCU_RESETz inactive (high) to RESETSTATz inactive (high) 3900*S(1)   ns
S = MCU_OSC0_XI/XO clock period.
GUID-20210225-CA0I-3MDC-C0LG-T6MMF6TKLZJZ-low.gif Figure 7-14 MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching Characteristics
Table 7-12 RESET_REQz Timing Requirements see Figure 7-15
NO. MIN MAX UNIT
RST27 tw(RESET_REQzL)(1) Pulse Width minimum, RESET_REQz active (low) 1200 ns
Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-13 RESET_REQz initiates; RESETSTATz Switching Characteristics see Figure 7-15
NO. PARAMETER MODE MIN MAX UNIT
RST28 td(RESET_REQzL-RESETSTATzL) Delay time, RESET_REQz active (low) to RESETSTATz active (low) software control of
SOC_WARMRST_ISO_DONE_Z
T(1)  
CTRLMMR_WKUP_MAIN_WARM
_RST_CTRL[0].SOC_
WARMRST_ISO_DONE_Z = 0
740 ns
RST29 td(RESET_REQzH-RESETSTATzH) Delay time, RESET_REQz inactive (high) to RESETSTATz inactive (high) 2650*S(2)   ns
T = Reset Isolation Time (Software Dependent).
S = MCU_OSC0_XI/XO clock period.
GUID-20210225-CA0I-XJHR-RFCB-PCCCWHCTZ6TX-low.gif Figure 7-15 RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics
Table 7-14 EMUx Timing Requirements see Figure 7-16
NO.   MIN MAX UNIT
RST30 tsu(EMUx-MCU_PORz) Setup time, EMU[1:0] before MCU_PORz inactive (high) 3*S(1) ns
RST31 th(MCU_PORz - EMUx) Hold time, EMU[1:0] after MCU_PORz inactive (high) 10 ns
S = MCU_OSC0_XI/XO clock period.
GUID-20210225-CA0I-Z5HH-ZNJJ-CNQ5H27CFLWC-low.gif Figure 7-16 EMUx Timing Requirements
Table 7-15 MCU_BOOTMODE Timing Requirements see Figure 7-17
NO. MIN MAX UNIT
RST32 tsu(MCU_BOOTMODE-MCU_PORz) Setup time, MCU_BOOTMODE[09:00] before MCU_PORz high 3*S(1) ns
RST33 th(MCU_PORz - MCU_BOOTMODE) Hold time, MCU_BOOTMODE[09:00] after MCU_ PORz high 0 ns
S = MCU_OSC0_XI/XO clock period.
GUID-20221019-SS0I-LWMW-3RR9-JKJVNJCFD25H-low.gif Figure 7-17 MCU_BOOTMODE Timing Requirements
Table 7-16 BOOTMODE Timing Requirements see Figure 7-18
NO.   MIN MAX UNIT
RST34 tsu(BOOTMODE-PORz) Setup time, BOOTMODE[7:0] before PORz high 3*S(1)   ns
RST35 th(PORz - BOOTMODE) Hold time, BOOTMODE[7:0] after PORz high 0   ns
S = MCU_OSC0_XI/XO clock period.
GUID-20221019-SS0I-H8WN-WQJ8-ZK39CDSDF2G9-low.gif Figure 7-18 BOOTMODE Timing Requirements