SLVSCX2B August   2015  – February 2016 DRV8305

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements (Slave Mode Only)
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Three-Phase Gate Driver
      2. 7.3.2 INHx/INLx: Gate Driver Input Modes
      3. 7.3.3 VCPH Charge Pump: High-Side Gate Supply
      4. 7.3.4 VCP_LSD LDO: Low-Side Gate Supply
      5. 7.3.5 GHx/GLx: Half-Bridge Gate Drivers
        1. 7.3.5.1 IDRIVE: Gate Driver Output Current
        2. 7.3.5.2 TDRIVE: Gate Driver State Machine
        3. 7.3.5.3 CSAs: Current Shunt Amplifiers
      6. 7.3.6 DVDD and AVDD: Internal Voltage Regulators
      7. 7.3.7 VREG: Voltage Regulator Output
      8. 7.3.8 Protection Features
        1. 7.3.8.1 Fault and Warning Classification
        2. 7.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)
        3. 7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)
          1. 7.3.8.3.1 MOSFET dV/dt Turn On Protection (TDRIVE)
          2. 7.3.8.3.2 MOSFET Gate Drive Protection (GDF)
        4. 7.3.8.4 Low-Side Source Monitors (SNS_OCP)
        5. 7.3.8.5 Fault and Warning Operating Modes
      9. 7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
        1. 7.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection
        2. 7.3.9.2 Reverse Supply Protection
        3. 7.3.9.3 MCU Watchdog
        4. 7.3.9.4 VREG Undervoltage (VREG_UV)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
      4. 7.4.4 Sleep State
      5. 7.4.5 Limp Home or Fail Code Operation
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Status Registers
        1. 7.6.1.1 Warning and Watchdog Reset (Address = 0x1)
        2. 7.6.1.2 OV/VDS Faults (Address = 0x2)
        3. 7.6.1.3 IC Faults (Address = 0x3)
        4. 7.6.1.4 VGS Faults (Address = 0x4)
      2. 7.6.2 Control Registers
        1. 7.6.2.1 HS Gate Drive Control (Address = 0x5)
        2. 7.6.2.2 LS Gate Drive Control (Address = 0x6)
        3. 7.6.2.3 Gate Drive Control (Address = 0x7)
        4. 7.6.2.4 IC Operation (Address = 0x9)
        5. 7.6.2.5 Shunt Amplifier Control (Address = 0xA)
        6. 7.6.2.6 Voltage Regulator Control (Address = 0xB)
        7. 7.6.2.7 VDS Sense Control (Address = 0xC)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current
        2. 8.2.2.2 MOSFET Slew Rates
        3. 8.2.2.3 Overcurrent Protection
        4. 8.2.2.4 Current Sense Amplifiers
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8305 is a gate driver IC designed to drive a 3-phase BLDC motor in combination with external power MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, three current shunt amplifiers, adjustable slew rate control, logic LDO, and a suite of protection features.

8.2 Typical Application

The following design is a common application of the DRV8305.

DRV8305 typ_app_lvscx2.gif Figure 18. Typical Application Schematic

8.2.1 Design Requirements

Table 20. Design Parameters

DESIGN PARAMETER REFERENCE VALUE
Supply voltage PVDD 12 V
Motor winding resistance MR 0.5 Ω
Motor winding inductance ML 0.28 mH
Motor poles MP 16 poles
Motor rated RPM MRPM 2000 RPM
Number of MOSFETs switching NSW 6
Switching frequency fSW 45 kHz
IDRIVEP IDRIVEP 50 mA
IDRIVEN IDRIVEN 60 mA
MOSFET QG Qg 36 nC
MOSFET QGD QGD 9 nC
MOSFET RDS(on) RDS(on) 4.1 mΩ
Target full-scale current IMAX 30 A
Sense resistor RSENSE 0.005 Ω
VDS trip level VDS_LVL 0.197 V
Amplifier bias VBIAS 1.65 V
Amplifier gain Gain 10 V/V

8.2.2 Detailed Design Procedure

8.2.2.1 Gate Drive Average Current

The gate drive supply (VCP) of the DRV8305 is capable of delivering up to 30 mA (RMS) of current to the external power MOSFETs. The charge pump directly supplies the high-side N-channel MOSFETs and a 10-V LDO powered from VCP supplies the low-side N-channel MOSFETs. The designer can determine the approximate RMS load on the gate drive supply through the following equation.

Equation 2. Gate Drive RMS Current = MOSFET Qg × Number of Switching MOSFETs × Switching Frequency

Example: 36 nC (QG) × 6 (NSW) × 45 kHz (fSW) = 9.72 mA

Note that this is only a first-order approximation.

8.2.2.2 MOSFET Slew Rates

The rise and fall times of the external power MOSFET can be adjusted through the use of the DRV8305 IDRIVE setting. A higher IDRIVE setting will charge the MOSFET gate more rapidly where a lower IDRIVE setting will charge the MOSFET gate more slowly. System testing requires fine tuning to the desired slew rate, but a rough first-order approximation can be calculated as shown in the following.

Equation 3. MOSFET Slew Rate = MOSFET QGD / IDRIVE Setting

Example: 9 nC (QGD) / 50 mA (IDRIVEP) = 180 ns

8.2.2.3 Overcurrent Protection

The DRV8305 provides overcurrent protection for the external power MOSFETs through the use of VDS monitors for both the high-side and low-side MOSFETs. These are intended for protecting the MOSFET in overcurrent conditions and are not for precise current regulation.

The overcurrent protection works by monitoring the VDS voltage drop of the external MOSFETs and comparing it against the internal VDS_LEVEL set through the SPI registers. The high-side VDS is measured across the VDRAIN and SH_X pins. The low-side VDS is measured across the SH_X and SL_X pins. If the VDS voltage exceeds the VDS_LEVEL value, the DRV8305 will take action according to the VDS_MODE register.

The overcurrent trip level can be determined with the MOSFET RDS(on) and the VDS_LEVEL setting.

Equation 4. Overcurrent Trip = VDS Level (VDS_LVL) / MOSFET RDS(on) (RDS(on))

Example: 0.197 V (VDS_LVL) / 4.1 mΩ (RDS(ON)) = 48 A

8.2.2.4 Current Sense Amplifiers

The DRV8305 provides three bidirectional low-side current shunt amplifiers. These can be used to sense the current flowing through each half-bridge. If individual half-bridge sensing is not required, a single current shunt amplifier can be used to measure the sum of the half-bridge current. Use this simple procedure to correctly configure the current shunt amplifiers.

  1. Determine the peak current that the motor will demand (IMAX). This demand depends on the motor parameters and the application requirements. IMAX in this example is 14 A.
  2. Determine the available voltage output range for the current shunt amplifiers. This will be the ± voltage around the amplifier bias voltage (VBIAS). In this case VBIAS = 1.65 V and a valid output voltage is 0 to 3.3 V. This gives an output range of ±1.65 V.
  3. Determine the sense resistor value and amplifier gain settings. The sense resistor value and amplifier gain have common tradeoffs. The larger the sense resistor value, the better the resolution of the half-bridge current. This comes at the cost of additional power dissipated from the sense resistor. A larger gain value allows for the use of a smaller resolution, but at the cost of increased noise in the output signal and a longer settling time. This example uses a 5-mΩ sense resistor and the minimum gain setting of the DRV8305 (10 V/V). These values allow the current shunt amplifiers to measure ±33 A across the sense resistor.

8.2.3 Application Curves

DRV8305 gate_drive_20_SLVSCX2.gif
Figure 19. Gate Drive 20% Duty Cycle
DRV8305 motor_spinning_1000_SLVSCX2.gif
Figure 21. Motor Spinning 1000 RPM
DRV8305 gate_drive_80_SLVSCX2.gif
Figure 20. Gate Drive 80% Duty Cycle
DRV8305 motor_spinning_2000_SLVSCX2.gif
Figure 22. Motor Spinning 2000 RPM