SNLS043H May   2000  – January 2016 DS90CR216A , DS90CR286A , DS90CR286A-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: Receiver
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
        1. 7.3.1.1 LVDS Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Cables
        2. 8.2.2.2 Bit Resolution and Operating Frequency Compatibility
        3. 8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
        4. 8.2.2.4 RSKM Interoperability
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90CR286A and DS90CR216A are designed for a wide variety of data transmission applications. The use of serialized LVDS data lines in these applications allows for efficient signal transmission over a narrow bus width, thereby reducing cost, power, and space.

8.2 Typical Applications

DS90CR216A DS90CR286A DS90CR286A-Q1 286_typ_blk_diagram.gif Figure 19. Typical DS90CR286A Application Block Diagram
DS90CR216A DS90CR286A DS90CR286A-Q1 216_typ_blk_diagram.gif Figure 20. Typical DS90CR216A Application Block Diagram

8.2.1 Design Requirements

For this design example, ensure that the following requirements are observed.

Table 1. Design Parameters

DESIGN PARAMETER DESIGN REQUIREMENTS
Operating Frequency LVDS clock must be within 20-66 MHz.
Bit Resolution DS90CR286A: No higher than 24 bpp. The maximum supported resolution is 8-bit RGB.
DS90CR216A: No higher than 18 bpp. The maximum supported resolution is 6-bit RGB.
Bit Data Mapping Determine the appropriate mapping required by the panel display following the DS90CR286A or DS90CR216A outputs.
RSKM (Receiver Skew Margin) Ensure that there is acceptable margin between Tx pulse position and Rx strobe position.
Input Termination for RxIN± 100 Ω ± 10% resistor across each LVDS differential pair. Place as close as possible to IC input pins.
RxIN± Board Trace Impedance Design differential trace impedance with 100 Ω ± 5%
LVCMOS Outputs If unused, leave pins floating. Series resistance on each LVCMOS output optional to reduce reflections from long board traces. If used, 33-Ω series resistance is typical.
DC Power Supply Coupling Capacitors Use a 0.1-µF capacitor to minimize power supply noise. Place as close as possible to VCC pins.

8.2.2 Detailed Design Procedure

To design with the DS90CR286A or DS90CR216A, determine the following:

  • Cable Interface
  • Bit Resolution and Operating Frequency
  • Bit Mapping from Receiver to Endpoint Panel Display
  • RSKM Interoperability with Transmitter Pulse Position Margin

8.2.2.1 Cables

A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The DS90CR216A requires four pairs of signal wires and the DS90CR286A requires five pairs of signal wires. The ideal cable interface has a constant 100-Ω differential impedance throughout the path. It is also recommended that cable skew remain below 150 ps (assuming 66 MHz clock rate) to maintain a sufficient data sampling window at the receiver.

Depending upon the application and data rate, the interconnecting media between Tx and Rx may vary. For example, for lower data rate (clock rate) and shorter cable lengths (< 2m), the media electrical performance is less critical. For higher speed or long distance applications, the media's performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs). For example, twin-coax cables have been demonstrated at distances as long as five meters and with the maximum data transfer of 1.386 Gbps (DS90CR216A) and 1.848 Gbps (DS90CR286A).

8.2.2.2 Bit Resolution and Operating Frequency Compatibility

The bit resolution of the endpoint panel display reveals whether there are enough bits available in the DS90CR286A or DS90CR216A to output the required data per pixel. The DS90CR286A has 28 parallel LVCMOS outputs and can therefore provide a bit resolution up to 24 bpp (bits per pixel). In each clock cycle, the remaining bits are the three control signals (HSync, VSync, DE) and one spare bit. The DS90CR216A has 21 parallel LVCMOS outputs and can therefore provide a bit resolution up to 18 bpp (bits per pixel). In each clock cycle, the remaining bits are the three control signals (HSync, VSync, DE).

The number of pixels per frame and the refresh rate of the endpoint panel display indicate the required operating frequency of the deserializer clock. To determine the required clock frequency, refer to the following formula:

Equation 1. f_Clk = [H_Active + H_Blank] × [V_Active + V_Blank] × f_Vertical

where

  • H_Active = Active Display Horizontal Lines
  • H_Blank = Blanking Period Horizontal Lines
  • V_Active = Active Display Vertical Lines
  • V_Blank = Blanking Period Vertical Lines
  • f_Vertical = Refresh Rate (in Hz)
  • f_Clk = Operating Frequency of LVDS clock

In each frame, there is a blanking period associated with horizontal rows and vertical columns that are not actively displayed on the panel. These blanking period pixels must be included to determine the required clock frequency. Consider the following example to determine the required LVDS clock frequency:

  • H_Active = 640
  • H_Blank = 40
  • V_Active = 480
  • V_Blank = 41
  • f_Vertical = 59.95 Hz

Thus, the required operating frequency is determined below:

Equation 2. [640 + 40] x [480 + 41] x 59.95 = 21239086 Hz ≈ 21.24 MHz

Since the operating frequency for the PLL in the DS90CR286A and DS90CR216A ranges from 20-66 MHz, the DS90CR286A and DS90CR216A can support a panel display with the aforementioned requirements.

If the specific blanking interval is unknown, the number of pixels in the blanking interval can be approximated to 20% of the active pixels. The following formula can be used as a conservative approximation for the operating LVDS clock frequency:

Equation 3. f_Clk ≈ H_Active x V_Active x f_Vertical x 1.2

Using this approximation, the operating frequency for the example in this section is estimated below:

Equation 4. 640 x 480 x 59.95 x 1.2 = 22099968 Hz ≈ 22.10 MHz

8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display

Ensure that the LVCMOS outputs are mapped to align with the endpoint display RGB mapping requirements following the deserializer. Two popular mapping topologies for 8-bit RGB data are shown below:

  1. LSBs are mapped to RxIN3±.
  2. MSBs are mapped to RxIN3±.

The following tables depict how these two popular topologies can be mapped to the DS90CR286A outputs.

Table 2. 8-Bit Color Mapping with LSBs on RxIN3±

LVDS INPUT CHANNEL LVDS BIT STREAM POSITION LVCMOS OUTPUT CHANNEL COLOR MAPPING COMMENTS
RxIN0 TxIN0 RxOUT0 R2
TxIN1 RxOUT1 R3
TxIN2 RxOUT2 R4
TxIN3 RxOUT3 R5
TxIN4 RxOUT4 R6
TxIN6 RxOUT6 R7 MSB
RxIN1 TxIN7 RxOUT7 G2
TxIN8 RxOUT8 G3
TxIN9 RxOUT9 G4
TxIN12 RxOUT12 G5
TxIN13 RxOUT13 G6
TxIN14 RxOUT14 G7 MSB
TxIN15 RxOUT15 B2
TxIN18 RxOUT18 B3
RxIN2 TxIN19 RxOUT19 B4
TxIN20 RxOUT20 B5
TxIN21 RxOUT21 B6
TxIN22 RxOUT22 B7 MSB
TxIN24 RxOUT24 HSYNC Horizontal Sync
TxIN25 RxOUT25 VSYNC Vertical Sync
TxIN26 RxOUT26 DE Data Enable
RxIN3 TxIN27 RxOUT27 R0 LSB
TxIN5 RxOUT5 R1
TxIN10 RxOUT10 G0 LSB
TxIN11 RxOUT11 G1
TxIN16 RxOUT16 B0 LSB
TxIN17 RxOUT17 B1
TxIN23 RxOUT23 GP General Purpose

Table 3. 8-Bit Color Mapping with MSBs on RxIN3±

LVDS INPUT CHANNEL LVDS BIT STREAM POSITION LVCMOS OUTPUT CHANNEL COLOR MAPPING COMMENTS
RxIN0 TxIN0 RxOUT0 R0 LSB
TxIN1 RxOUT1 R1
TxIN2 RxOUT2 R2
TxIN3 RxOUT3 R3
TxIN4 RxOUT4 R4
TxIN6 RxOUT6 R5
RxIN1 TxIN7 RxOUT7 G0 LSB
TxIN8 RxOUT8 G1
TxIN9 RxOUT9 G2
TxIN12 RxOUT12 G3
TxIN13 RxOUT13 G4
TxIN14 RxOUT14 G5
TxIN15 RxOUT15 B0 LSB
TxIN18 RxOUT18 B1
RxIN2 TxIN19 RxOUT19 B2
TxIN20 RxOUT20 B3
TxIN21 RxOUT21 B4
TxIN22 RxOUT22 B5
TxIN24 RxOUT24 HSYNC Horizontal Sync
TxIN25 RxOUT25 VSYNC Vertical Sync
TxIN26 RxOUT26 DE Data Enable
RxIN3 TxIN27 RxOUT27 R6
TxIN5 RxOUT5 R7 MSB
TxIN10 RxOUT10 G6
TxIN11 RxOUT11 G7 MSB
TxIN16 RxOUT16 B6
TxIN17 RxOUT17 B7 MSB
TxIN23 RxOUT23 GP General Purpose

In either the case where the DS90CR216A is used or the DS90CR286A must support 18 bpp, Table 2 is commonly used. With this mapping, MSBs of RGB data are retained on RXIN0±, RXIN1±, and RXIN2± while the two LSBs for the original 8-bit RGB resolution are ignored from RxIN3±.

8.2.2.4 RSKM Interoperability

One of the most important factors when designing the receiver into a system application is assessing how much RSKM (Receiver Skew Margin) is available. In each LVDS clock cycle, the LVDS data stream carries seven serialized data bits. Ideally, the Transmit Pulse Position for each bit will occur every (n x T)/7 seconds, where n = Bit Position and T = LVDS Clock Period. Likewise, ideally the Receive Strobe Position for each bit will occur every ((n + 0.5) x T)/7 seconds. However, due to the effects of cable skew, clock jitter, and ISI, both LVDS transmitter and receiver in real systems will have a minimum and maximum pulse and strobe position, respectively, for each bit position. This concept is illustrated in Figure 21:

DS90CR216A DS90CR286A DS90CR286A-Q1 RSKM_TI_Notation_1.gif Figure 21. RSKM Measurement Example

All left and right margins for Bits 0-6 must be considered in order to determine the absolute minimum for the whole LVDS bit stream. This absolute minimum corresponds to the RSKM.

To improve RSKM performance between LVDS transmitter and receiver, designers often either advance or delay the LVDS clock compared to the LVDS data. Moving the LVDS clock compared to the LVDS data can improve the location of the setup and hold time for the transmitter compared to the setup and hold time for the receiver.

If there is less left bit margin than right bit margin, the LVDS clock can be delayed so that the Rx strobe position for incoming data appears to be delayed. If there is less right bit margin than left bit margin, all the LVDS data pairs can be delayed uniformly so that the LVDS clock and Rx strobe position for incoming data appear to advance. To delay an LVDS data or clock pair, designers either add more PCB trace length or install a capacitor between the LVDS transmitter and receiver. It is important to note that when using these techniques, all serialized bit positions are shifted right or left uniformly.

When designing the DS90CR286A or DS90CR216A receiver with a third-party OpenLDI transmitter, users must calculate the skew margin budget (RSKM) based on the Tx pulse position and the Rx strobe position to ensure error-free transmission. For more information about calculating RSKM, refer to Application Note SNLA249.

8.2.3 Application Curves

The following application curves are examples taken with a DS90C385 serializer interfacing to a DS90CR286A deserializer in nominal temperature (25ºC) at an operating frequency of 66 MHz.

DS90CR216A DS90CR286A DS90CR286A-Q1 clock_lvds_data.gif Figure 22. LVDS RxIN0± aligned with LVCMOS RxCLKOUT
DS90CR216A DS90CR286A DS90CR286A-Q1 RisingEdge_to_RxStrobe.gif Figure 24. RxOUT Strobe on Rising Edge of RxCLKOUT
DS90CR216A DS90CR286A DS90CR286A-Q1 LVDS_CLK_v_LVCMOS_CLK.gif Figure 23. LVDS CLKIN aligned with LVCMOS RxCLKOUT
DS90CR216A DS90CR286A DS90CR286A-Q1 PRBS7_66MHz_AdjacentChannels.gif Figure 25. PRBS-7 Output on RxOUT Channels