JAJSKM3A november   2020  – november 2020 DS90UB633A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Serializer Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB633A/662
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS V(VDDIO) Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB633A/662 Operation With External Oscillator as Reference Clock
      2. 7.4.2 DS90UB633A/662 Operation With Pixel Clock From Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built-In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 IDX Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Interconnect Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tLHT CML low-to-high transition time RL = 100 Ω Figure 6-1 150 330 ps
tHLT CML high-to-low transition time RL = 100 Ω Figure 6-1 150 330 ps
tDIS Data input Setup to PCLK Serializer data inputs Figure 6-8 2 ns
tDIH Data input Hold from PCLK 2 ns
tPLD Serializer PLL lock time.(1)(2) RL = 100 Ω Figure 6-9 1 2
tSD Serializer delay(2) RT = 100 Ω, 10–bit mode Register 0x03h b[0] (TRFB = 1) Figure 6-10 32.5T 38T 44T
RT = 100 Ω, 12–bit mode Register 0x03h b[0] (TRFB = 1) Figure 6-10 11.75T 13T 15T
tJIND Serializer output deterministic jitter(3)(4)(5) PRBS-7 test pattern, CDR PLL Loop BW = ƒ/15, BER = 1E-10 DOUT± 0.17 UI
tJINR Serializer output random jitter(3)(4)(5) PRBS-7 test pattern, CDR PLL Loop BW = ƒ/15, BER = 1E-10 DOUT± 0.016 UI
tJINT Peak-to-peak serializer output total jitter(3)(5)(6) PRBS-7 test pattern, CDR PLL Loop BW = ƒ/15, BER = 1E-10 DOUT± 0.4 UI
λSTXBW Serializer jitter transfer function –3 dB bandwidth 10–bit mode PCLK = 100 MHz, Default registers 2.2 MHz
12–bit mode PCLK = 100 MHz, Default registers 2.2
δSTX Serializer jitter Transfer Function (peaking) 10–bit mode PCLK = 100 MHz, Default registers 1.06 dB
12–bit mode PCLK = 100 MHz, Default registers 1.09
δSTXf Serializer jitter transfer function (peaking frequency) 10–bit mode PCLK = 100 MHz, Default registers 400 kHz
12–bit mode PCLK = 100 MHz, Default registers 500
(1) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(2) Specification is verified by design.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at Section 6.3 at the time of product characterization and are not verified.
(4) Specification is verified by characterization and is not tested in production.
(5) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 × 28 )
12-bit mode: 1 UI = 1 / ( PCLK_Freq. × 2/3 × 28 )
(6) Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input.