JAJSGJ0D
October 2014 – February 2022
DS90UH948-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
AC Electrical Characteristics
6.7
Timing Requirements for the Serial Control Bus
6.8
Switching Characteristics
6.9
Timing Diagrams and Test Circuits
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
High-Speed Forward Channel Data Transfer
7.3.2
Low-Speed Back Channel Data Transfer
7.3.3
FPD-Link III Port Register Access
7.3.4
Oscillator Output
7.3.5
Clock and Output Status
7.3.6
LVCMOS VDDIO Option
7.3.7
Power Down (PDB)
7.3.8
Interrupt Pin — Functional Description and Usage (INTB_IN)
7.3.9
General-Purpose I/O (GPIO)
7.3.9.1
GPIO[3:0] and D_GPIO[3:0] Configuration
7.3.9.2
Back Channel Configuration
7.3.9.3
GPIO Register Configuration
7.3.10
SPI Communication
7.3.10.1
SPI Mode Configuration
7.3.10.2
Forward Channel SPI Operation
7.3.10.3
Reverse Channel SPI Operation
7.3.11
Backward Compatibility
7.3.12
Adaptive Equalizer
7.3.12.1
Transmission Distance
7.3.12.2
Adaptive Equalizer Algorithm
7.3.12.3
AEQ Settings
7.3.12.3.1
AEQ Start-Up and Initialization
7.3.12.3.2
AEQ Range
7.3.12.3.3
AEQ Timing
7.3.13
I2S Audio Interface
7.3.13.1
I2S Transport Modes
7.3.13.2
I2S Repeater
7.3.13.3
I2S Jitter Cleaning
7.3.13.4
MCLK
7.3.14
HDCP Repeater
7.3.14.1
HDCP
7.3.14.2
HDCP Repeater
7.3.14.2.1
Repeater Configuration
7.3.14.2.2
Repeater Connections
7.3.14.2.2.1
Repeater Fan-Out Electrical Requirements
7.3.14.2.2.2
HDCP I2S Audio Encryption
7.3.15
Built-In Self Test (BIST)
7.3.15.1
BIST Configuration and Status
7.3.15.1.1
Sample BIST Sequence
7.3.15.2
Forward Channel and Back Channel Error Checking
7.3.16
Internal Pattern Generation
7.4
Device Functional Modes
7.4.1
Configuration Select MODE_SEL[1:0]
7.4.1.1
1-Lane FPD-Link III Input, Single Link OpenLDI Output
7.4.1.2
1-Lane FPD-Link III Input, Dual Link OpenLDI Output
7.4.1.3
2-Lane FPD-Link III Input, Dual Link OpenLDI Output
7.4.1.4
2-Lane FPD-Link III Input, Single Link OpenLDI Output
7.4.1.5
1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
7.4.2
MODE_SEL[1:0]
7.4.2.1
Dual Swap
7.4.3
OpenLDI Output Frame and Color Bit Mapping Select
7.5
Image Enhancement Features
7.5.1
White Balance
7.5.2
LUT Contents
7.5.3
Enabling White Balance
7.5.3.1
LUT Programming Example
7.5.4
Adaptive Hi-FRC Dithering
7.6
Programming
7.6.1
Serial Control Bus
7.6.2
Multi-Controller Arbitration Support
7.6.3
I2C Restrictions on Multi-Controller Operation
7.6.4
Multi-Controller Access to Device Registers for Newer FPD-Link III Devices
7.6.5
Multi-Controller Access to Device Registers for Older FPD-Link III Devices
7.6.6
Restrictions on Control Channel Direction for Multi-Controller Operation
7.7
Register Maps
7.7.1
DS90UH948-Q1 Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
FPD-Link III Interconnect Guidelines
8.2.2.2
AV Mute Prevention
8.2.2.3
Prevention of I2C Errors During Abrupt System Faults
8.2.3
Application Curves
9
Power Supply Recommendations
9.1
Power-Up Requirements and PDB Pin
9.2
Power Sequence
10
Layout
10.1
Layout Guidelines
10.2
Ground
10.3
Routing FPD-Link III Signal Traces
10.4
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
ドキュメントの更新通知を受け取る方法
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
NKD|64
MPQS032B
サーマルパッド・メカニカル・データ
NKD|64
QFND765
発注情報
jajsgj0d_oa
jajsgj0d_pm
11.6
用語集
テキサス・インスツルメンツ用語集
この用語集には、用語や略語の一覧および定義が記載されています。