JAJSES7A February   2018  – April  2018 ESD204

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings -JEDEC Specifications
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 nA, across operating temperature range -3.6 3.6 V
VBRF Positive Breakdown Voltage, Each IO Pin to GND (1) IIO = 1 mA 5 7.9 V
VBRR Negative Breakdown Voltage, Each IO Pin to GND (1) IIO = -1 mA, -7.9 -5 V
VHOLD Positive Holding Voltage, Each IO pin to GND  (2) IIO = 1 mA 6.2 V
VHOLD-NEG Negative Holding Voltage, Each IO  pin to GND (2) IIO = -1 mA -6.2 V
VCLAMP Clamping voltage Surge IPP = 5.5 A, Each IO pin to GND, GND to Each IO pin, tp=8/20 μs 8.5 V
TLP IPP = 5 A,  Each IO pin to GND, GND to Each IO pin, tp=10/100 ns 8.2 V
TLP IPP = 16 A, Each IO pin to GND, GND to Each IO pin, tp=10/100 ns 11.5 V
RDYN Dynamic resistance Each IO Pin to GND, TLP tp=10/100 ns  0.3 Ω
GND to Each IO Pin, TLP tp=10/100 ns 0.3
CLINE Line capacitance, any IO to GND VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 0.55 0.65 pF
ΔCLINE Variation of line capacitance CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 0.02 0.07 pF
CCROSS Line-to-line capacitance VIO = 0 V, Vrms = 30 mV, f = 1 MHz 0.25 0.35 pF
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.