SLLSEK8C January   2015  – April 2015 ISO7320C , ISO7320FC , ISO7321C , ISO7321FC

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, 5 V
    6. 6.6 Electrical Characteristics, 3.3 V
    7. 6.7 Switching Characteristics, 5 V
    8. 6.8 Switching Characteristics, 3.3 V
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Voltage Feature Description
        1. 8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package
        2. 8.3.1.2 Insulation Characteristics
        3. 8.3.1.3 Regulatory Information
        4. 8.3.1.4 Safety Limiting Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Typical Supply Current Equations
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Performance Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 PCB Material
    2. 11.2 Layout Guidelines
    3. 11.3 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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メカニカル・データ(パッケージ|ピン)
  • D|8
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage, VCC1 , VCC2(2) –0.5 6 V
Voltage (2) INx, OUTx –0.5 VCC+ 0.5(3) V
Output current, IO ±15 mA
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

VALUE UNIT
VESD Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VCC1, VCC2 Supply voltage 3 5.5 V
IOH High-level output current –4 mA
IOL Low-level output current 4 mA
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0 0.8 V
tui Input pulse duration 40 ns
1 / tui Signaling rate 0 25 Mbps
TJ(1) Junction temperature 136 °C
TA Ambient temperature -40 25 125 °C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.

6.4 Thermal Information

THERMAL METRIC(1) D PACKAGE UNIT
(8) PINS
RθJA Junction-to-ambient thermal resistance 121 °C/W
RθJCtop Junction-to-case (top) thermal resistance 67.9
RθJB Junction-to-board thermal resistance 61.6
ψJT Junction-to-top characterization parameter 21.5
ψJB Junction-to-board characterization parameter 61.1
RθJCbot Junction-to-case (bottom) thermal resistance N/A
PD (ISO7320) Maximum power dissipation by ISO7320 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5 MHz 50% duty-cycle square wave 56 mW
PD1 (ISO7320) Maximum power dissipation by side-1 of ISO7320 15
PD2 (ISO7320) Maximum power dissipation by side-2 of ISO7320 41
PD (ISO7321) Maximum power dissipation by ISO7321 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5 MHz 50% duty-cycle square wave 67 mW
PD1 (ISO7321) Maximum power dissipation by side-1 of ISO7321 33.5
PD2 (ISO7321) Maximum power dissipation by side-2 of ISO7321 33.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics, 5 V

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1)– 0.5 4.7 V
IOH = –20 μA; see Figure 11 VCCO(1) – 0.1 5
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
IOL = 20 μA; see Figure 11 0 0.1
VI(HYS) Input threshold voltage hysteresis 460 mV
IIH High-level input current IN = VCC 10 μA
IIL Low-level input current IN = 0 V –10 μA
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 13. 25 65 kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7320
ICC1 Supply current for VCC1 and VCC2 DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
0.4 0.9 mA
ICC2 2 3.2
ICC1 10 Mbps CL = 15pF 0.8 1.4
ICC2 3.2 4.4
ICC1 25 Mbps CL = 15pF 1.4 2.3
ICC2 4.9 6.8
ISO7321
ICC1 , ICC2 Supply current for VCC1 and VCC2 DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
1.7 2.8 mA
ICC1 , ICC2 10 Mbps CL = 15pF 2.5 3.7
ICC1 , ICC2 25 Mbps CL = 15pF 3.7 5.4
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.

6.6 Electrical Characteristics, 3.3 V

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1)– 0.5 3 V
IOH = –20 μA; see Figure 11 VCCO(1)– 0.1 3.3
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
IOL = 20 μA; see Figure 11 0 0.1
VI(HYS) Input threshold voltage hysteresis 450 mV
IIH High-level input current IN = VCC 10 μA
IIL Low-level input current IN = 0 V -10 μA
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 13 25 50 kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7320
ICC1 Supply current for VCC1 and VCC2 DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
0.2 0.5 mA
ICC2 1.5 2.5
ICC1 10 Mbps CL = 15pF 0.5 0.8
ICC2 2.2 3.2
ICC1 25 Mbps CL = 15pF 0.9 1.4
ICC2 3.3 4.7
ISO7321
ICC1 , ICC2 Supply current for VCC1 and VCC2 DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
1.2 2 mA
ICC1 , ICC2 10 Mbps CL = 15pF 1.7 2.5
ICC1 , ICC2 25 Mbps CL = 15pF 2.5 3.6
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.

6.7 Switching Characteristics, 5 V

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 20 33 57 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 4 ns
tsk(o)(2) Channel-to-channel output skew time ISO7320 2 ns
ISO7321 17
tsk(pp)(3) Part-to-part skew time 23 ns
tr Output signal rise time See Figure 11 2.4 ns
tf Output signal fall time 2.1 ns
tfs Fail-safe output delay time from input power loss See Figure 12 7.5 μs
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.8 Switching Characteristics, 3.3 V

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT3
tPLH, tPHL Propagation delay time See Figure 11 22 37 66 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 3 ns
tsk(o)(2) Channel-to-channel output skew time ISO7320 3 ns
ISO7321 16
tsk(pp)(3) Part-to-part skew time 28 ns
tr Output signal rise time See Figure 11 3.1 ns
tf Output signal fall time 2.6 ns
tfs Fail-safe output delay time from input power loss See Figure 12 7.4 μs
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.9 Typical Characteristics

ISO7320C ISO7320FC ISO7321C ISO7321FC D001_SLLSEK8.gif
TA = 25°C CL = 15 pF
Figure 1. ISO7320 Supply Current vs Data Rate
ISO7320C ISO7320FC ISO7321C ISO7321FC D003_SLLSEK8.gif
TA = 25°C CL = 15 pF
Figure 3. ISO7321 Supply Current vs Data Rate
ISO7320C ISO7320FC ISO7321C ISO7321FC D005_SLLSEK8.gif
TA = 25°C
Figure 5. High-Level Output Voltage vs High-Level Output Current
ISO7320C ISO7320FC ISO7321C ISO7321FC D007_SLLSEK8.gif
Figure 7. Power Supply Under Voltage Threshold vs Free-Air Temperature
ISO7320C ISO7320FC ISO7321C ISO7321FC D009_SLLSEK8.gif
Figure 9. Input Glitch Suppression Time vs Free-Air Temperature
ISO7320C ISO7320FC ISO7321C ISO7321FC D002_SLLSEK8.gif
TA = 25°C No Load
Figure 2. ISO7320 Supply Current vs Data Rate
ISO7320C ISO7320FC ISO7321C ISO7321FC D004_SLLSEK8.gif
TA = 25°C No Load
Figure 4. ISO7321 Supply Current vs Data Rate
ISO7320C ISO7320FC ISO7321C ISO7321FC D006_SLLSEK8.gif
TA = 25°C
Figure 6. :Low-Level Output Voltage vs Low-Level Output Current
ISO7320C ISO7320FC ISO7321C ISO7321FC D008_SLLSEK8.gif
Figure 8. Propagation Delay Time vs Free-Air Temperature
ISO7320C ISO7320FC ISO7321C ISO7321FC D010_SLLSEK8.gif
Figure 10. Peak-to-Peak Output Jitter vs Data Rate