JAJSU29 March 2024 ISOUSB211-Q1
ADVANCE INFORMATION
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VBUS1 | — | Input Power Supply for Side 1. If a 4.25 V to 5.5 V (example USB power bus) supply is available connect it to VBUS1. In this case an internal LDO generates V3P3V1. Else, connect VBUS1 and V3P3V1 to an external 3.3 V power supply. |
2 | V3P3V1 | — | Power Supply for Side 1. If a 4.25 V to 5.5 V supply is connected to VBUS1 connect a bypass capacitor between V3P3V1 and GND1. In this case an internal LDO generates V3P3V1. Else, connect VBUS1 and V3P3V1 to an external 3.3 V power supply. |
3 | GND1 | — | Ground 1. Ground reference for Isolator Side 1. |
4 | V1P8V1 | — | Power Supply for Side 1. If a 2.4 V to 5.5 V supply is connected to VCC1 connect a bypass capacitor between V1P8V1 and GND1. In this case an internal LDO generates V1P8V1. Else, connect VCC1 and V1P8V1 to an external 1.8 V power supply. |
5 | VCC1 | — | Input Power Supply for Side 1. If a 2.4 V to 5.5 V (example USB power bus, or a DC-DC supply derived from USB power bus) supply is available connect it to VCC1. In this case an internal LDO generates V1P8V1. Else, connect VCC1 and V1P8V1 to an external 1.8 V power supply. |
6 | V2OK | O | High level on this pin indicates that side 2 is powered up. |
7 | UD- | I/O | Upstream facing port D-. |
8 | UD+ | I/O | Upstream facing port D+. |
9 | EQ10 | I | Equalization setting for Side 1, LSB. Logic Input. |
10 | EQ11 | I | Equalization setting for Side 1, MSB. Logic Input. |
11 | V1P8V1 | — | Connect pin 11 to pin 4, with local bypass capacitors near pin 11. |
12 | GND1 | — | Ground 1. Ground reference for Isolator Side 1. |
13 | CDPENZ1 | I | Active low singal. Enables CDP advertising on UD+/UD- pins. |
14 | NC | — | Leave floating or connect to V3P3V1. |
15 | NC | — | Leave floating or connect to V3P3V2. |
16 | CDPENZ2 | I | Active low singal. Enables CDP advertising on DD+/DD- pins. |
17 | GND2 | — | Ground 2. Ground reference for Isolator Side 2. |
18 | V1P8V2 | — | Connect pin 18 to pin 25, with local bypass capacitors near pin 18. |
19 | EQ21 | I | Equalization setting for Side 2, MSB. Logic Input. |
20 | EQ20 | I | Equalization setting for Side 2, LSB. Logic Input. |
21 | DD+ | I/O | Downstream facing port D+. |
22 | DD- | I/O | Downstream facing port D-. |
23 | V1OK | O | High level on this pin indicates that side 1 is powered up. |
24 | VCC2 | — | Input Power Supply for Side 2. If a 2.4 V to 5.5 V (example USB power bus, or a DC-DC supply derived from USB power bus) supply is available connect it to VCC2. In this case an internal LDO generates V1P8V2. Else, connect VCC2 and V1P8V2 to an external 1.8 V power supply. |
25 | V1P8V2 | — | Power Supply for Side 1. If a 2.4 V to 5.5 V supply is connected to VCC2 connect a bypass capacitor between V1P8V2 and GND2. In this case an internal LDO generates V1P8V2. Else, connect VCC2 and V1P8V2 to an external 1.8 V power supply. |
26 | GND2 | — | Ground 2. Ground reference for Isolator Side 2. |
27 | V3P3V2 | — | Power Supply for Side 2. If a 4.25 V to 5.5 V supply is connected to VBUS2 connect a bypass capacitor between V3P3V2 and GND1. In this case an internal LDO generates V3P3V2. Else, connect VBUS2 and V3P3V2 to an external 3.3 V power supply. |
28 | VBUS2 | — | Input Power Supply for Side 2. If a 4.25 V to 5.5 V (example USB power bus) supply is available connect it to VBUS2. In this case an internal LDO generates V3P3V2. Else, connect VBUS2 and V3P3V2 to an external 3.3 V power supply. |