A 0.1 µF capacitor should be used to bypass VDD. If multiple bypass capacitors are used in the system, then the smallest value capacitor should be placed as close as possible to the VDD pin. A ground plane is recommended to connect both the ground and the Die Attach Pad (DAP). If the supply ramp rate must be faster than 4.2 mV/µs the enable pin (EN) may be tied directly to VDD as shown in Figure 7-8.

Figure 7-8 Supply Connections for Fast Ramp Rate

For supply ramp rates slower than 4.2 mV/µs, an RC low pass filter must be added to the enable input (EN) as shown in Figure 7-9. Alternatively, the EN pin may be tied to a nanotimer or microcontroller to wake up the LDC0851 after VDD has ramped to its nominal value.

Figure 7-9 Supply Connections for Slow Ramp Rate

For applications that require low power, the EN pin may toggled with a GPIO or nanotimer to duty cycle the device and achieve ultra-low power consumption. Although the device may be power cycled to achieve a similar effect, some systems may not have a clean GPIO to supply the LDC0851 or the filtering on the supply may add a time constant delay which can make the use of the EN pin much more efficient and desirable for duty cycled applications. Refer to Low Power Operation for a detailed design example.