JAJSAS9F データシート

JAJSAS9F April 2007 – November 2023 LM25116

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PWP|20
- MHTS001G

サーマルパッド・メカニカル・データ

発注情報

5.5 Electrical Characteristics

The following conditions apply: T_J = 25°C, minimum and maximum limits apply over the junction temperature range of –40°C to 125°C and are provided for reference only, VIN = 24 V, VCC = 7.4 V, VCCX = 0 V, EN = 5 V, R_T = 16 kΩ, no load on LO and HO (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VIN SUPPLY
I_BIAS	VIN operating current	VCCX = 0 V		4.6	6.5	mA
I_BIASX	VIN operating current	VCCX = 5 V		1	1.5	mA
I_STDBY	VIN shutdown current	EN = 0 V		1	10	µA
VCC REGULATOR
V_CC(REG)	VCC regulation		7.1	7.4	7.7	V
	VCC LDO mode turnoff			10.6		V
	VCC regulation	VIN = 6 V	5	5.9	6	V
	VCC sourcing current limit	VCC = 0 V	15	26		mA
	VCCX switch threshold	VCCX rising	4.3	4.5	4.7	V
	VCCX switch hysteresis			0.25		V
	VCCX switch R_DS(ON)	ICCX = 10 mA		3.8	6.2	Ω
	VCCX leakage	VCCX = 0 V		–200		nA
	VCCX pulldown resistance	VCCX = 3 V		100		kΩ
	VCC undervoltage threshold	VCC rising	4.3	4.5	4.7	V
	VCC undervoltage hysteresis			0.2		V
	HB DC bias current	HB – SW = 15 V		125	200	µA
EN INPUT
VIL max	EN input low threshold				0.5	V
VIH min	EN input high threshold		3.3			V
	EN input bias current	VEN = 3 V	–7.5	–3	1	µA
	EN input bias current	VEN = 0.5 V	–1	0	1	µA
	EN input bias current	VEN = 42 V		15		µA
UVLO THRESHOLDS
	UVLO standby threshold	UVLO rising	1.17	1.215	1.262	V
	UVLO threshold hysteresis			0.1		V
	UVLO pullup current source	UVLO = 0 V		5.4		µA
	UVLO pulldown R_DS(ON)			80	210	Ω
SOFT START
	SS current source	SS = 0 V	8	11	14	µA
	SS diode emulation ramp disable threshold	SS rising		3		V
	SS to FB offset	FB = 1.25 V		160		mV
	SS output low voltage	Sinking 100 µA, UVLO = 0 V		45		mV
ERROR AMPLIFIER
V_REF	FB reference voltage	Measured at FB pin, FB = COMP	1.195	1.215	1.231	V
	FB input bias current	FB = 2 V		15	500	nA
	COMP sink and source current		3			mA
A_OL	DC gain			80		dB
f_BW	Unity gain bandwidth			3		MHz
PWM COMPARATORS
t_HO(OFF)	Forced HO off-time		320	450	580	ns
t_ON(min)	Minimum HO on-time	VIN = 42 V, C_RAMP = 50 pF		100		ns
OSCILLATOR
f_SW1	Frequency 1	RT = 16 kΩ	180	200	220	kHz
f_SW2	Frequency 2	RT = 5 kΩ	480	535	590	kHz
	RT output voltage		1.191	1.215	1.239	V
	RT sync positive threshold		3	3.5	4	V
CURRENT LIMIT
V_CS(TH)	Cycle-by-cycle sense voltage threshold (CSG to CS)	VCCX = 0 V, RAMP = 0 V	94	110	126	mV
V_CS(THX)	Cycle-by-cycle sense voltage threshold (CSG to CS)	VCCX = 5 V, RAMP = 0 V	105	122	139	mV
	CS bias current	CS = 42 V	–1		1	µA
	CS bias current	CS = 0 V		90	125	µA
	CSG bias current	CSG = 0 V		90	125	µA
	Current limit fault timer	R_T = 16 kΩ, 200 kHz, 256 clock cycles		1.28		ms
RAMP GENERATOR
I_R1	RAMP current 1	VIN = 40 V, VOUT=10 V	150	180	220	µA
I_R2	RAMP current 2	VIN = 10 V, VOUT = 10 V	21	28	35	µA
	VOUT bias current	VOUT = 36 V		200		µA
	RAMP output low voltage	VIN = 40 V, VOUT = 10 V		265		mV
DIODE EMULATION
	SW zero cross threshold			–6		mV
	DEMB output current	DEMB = 0 V, SS = 1.25 V	1.6	2.7	3.8	µA
	DEMB output current	DEMB =0 V, SS = 2.8 V	28	38	48	µA
	DEMB output current	DEMB = 0 V, SS = regulated by FB	45	65	85	µA
LO GATE DRIVER
V_OLL	LO low-state output voltage	I_LO = 10 mA		0.08	0.17	V
V_OHL	LO high-state output voltage	I_LO = -100 mA, V_OHL = V_CC – V_LO		0.25		V
	LO rise time	C-load = 1000 pF		18		ns
	LO fall time	C-load = 1000 pF		12		ns
I_OHL	Peak LO source current	V_LO = 0 V		1.8		A
I_OLL	Peak LO sink current	V_LO = VCC		3.5		A
HO GATE DRIVER
V_OLH	HO low-state output voltage	I_HO = 100 mA		0.17	0.27	V
V_OHH	HO high-state output voltage	I_HO = -100 mA, V_OHH = V_HB – V_HO		0.45		V
	HO rise time	C-load = 1000 pF		19		ns
	HO high-side fall time	C-load = 1000 pF		13		ns
I_OHH	Peak HO source current	V_HO = 0 V		1		A
I_OLH	Peak HO sink current	V_HO = VCC		2.2		A
	HB to SW undervoltage			3		V
THERMAL
T_SD	Thermal shutdown	Rising		170		°C
	Thermal shutdown hysteresis			15		°C