JAJSDG7 June   2017 LM25118-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO
      2. 7.3.2 Oscillator and Sync Capability
      3. 7.3.3 Error Amplifier and PWM Comparator
      4. 7.3.4 Ramp Generator
      5. 7.3.5 Current Limit
      6. 7.3.6 Maximum Duty Cycle
      7. 7.3.7 Soft Start
      8. 7.3.8 HO Output
      9. 7.3.9 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Mode Operation: VIN > VOUT
      2. 7.4.2 Buck-Boost Mode Operation: VIN ≊ VOUT
      3. 7.4.3 High Voltage Start-Up Regulator
      4. 7.4.4 Enable
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  R7 = RT
        3. 8.2.2.3  Inductor Selection - L1
        4. 8.2.2.4  R13 = RSENSE
        5. 8.2.2.5  C15 = CRAMP
        6. 8.2.2.6  Inductor Current Limit Calculation
        7. 8.2.2.7  C9 - C12 = Output Capacitors
        8. 8.2.2.8  D1
        9. 8.2.2.9  D4
        10. 8.2.2.10 C1 - C5 = Input Capacitors
        11. 8.2.2.11 C20
        12. 8.2.2.12 C8
        13. 8.2.2.13 C16 = CSS
        14. 8.2.2.14 R8, R9
        15. 8.2.2.15 R1, R3, C21
        16. 8.2.2.16 R2
        17. 8.2.2.17 Snubber
        18. 8.2.2.18 Error Amplifier Configuration
          1. 8.2.2.18.1 R4, C18, C17
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bias Power Dissipation Reduction
    2. 9.2 Thermal Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Power Supply Recommendations

9.1 Bias Power Dissipation Reduction

Buck or Buck-boost regulators operating with high-input voltage can dissipate an appreciable amount of power while supplying the required bias current of the IC. The VCC regulator must step-down the input voltage VIN to a nominal VCC level of 7 V. The large voltage drop across the VCC regulator translates into high power dissipation in the VCC regulator. There are several techniques that can significantly reduce this bias regulator power dissipation. Figure 27 and Figure 28 depict two methods to bias the IC, one from the output voltage and one from a separate bias supply. In the first case, the internal VCC regulator is used to initially bias the VCC pin. After the output voltage is established, the VCC pin bias current is supplied through the VCCX pin, which effectively disables the internal VCC regulator. Any voltage greater than 4 V can supply VCC bias through the VCCX pin. However, the voltage applied to the VCCX pin should never exceed 15 V. The voltage supplied through VCCX must be large enough to drive the switching MOSFETs into full saturation.

LM25118-Q1 30165151.gif Figure 27. VCC Bias From VOUT 4 V < VOUT < 15 V
LM25118-Q1 30165152.gif Figure 28. VCC Bias With Additional Bias Supply

9.2 Thermal Considerations

The highest power dissipating components are the two power MOSFETs, the recirculating diode, and the output diode. The easiest way to determine the power dissipated in the MOSFETs is to measure the total conversion losses (PIN - POUT), then subtract the power losses in the Schottky diodes, output inductor and any snubber resistors. An approximation for the recirculating Schottky diode loss is:

Equation 55. P = (1-D) × IOUT × VFWD

The boost diode loss is:

Equation 56. P = IOUT × VFWD

If a snubber is used, the power loss can be estimated with an oscilloscope by observation of the resistor voltage drop at both turnon and turnoff transitions. The LM25118-Q1 package has an exposed thermal pad to aid power dissipation. Selecting diodes with exposed pads will aid the power dissipation of the diodes as well. When selecting the MOSFETs, pay careful attention to RDS(ON) at high temperature. Also, selecting MOSFETs with low gate charge will result in lower switching losses.

See Application Notes AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages (SNVA183) and AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419) for thermal management techniques for use with surface mount components.