JAJSC48B May   2004  – December 2014 LM5102

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Startup and UVLO
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Dissipation Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 商標
    2. 11.2 静電気放電に関する注意事項
    3. 11.3 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

10 Pin
VSSOP (DGS), WSON (DPR)
Top View
LM5102 20088901.gif

Pin Functions

PIN TYPE(2) DESCRIPTION APPLICATION INFORMATION
NAME WSON(1),
VSSOP
HB 2 P High-side gate driver bootstrap rail Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal of bootstrap capacitor to HS. The Bootstrap capacitor should be placed as close to IC as possible.
HI 7 I High-side driver control input TTL compatible thresholds. Unused inputs should be tied to ground and not left open.
HO 3 O High-side gate driver output Connect to gate of high-side MOSFET with short low-inductance path.
HS 4 P High-side MOSFET source connection Connect bootstrap capacitor negative terminal and source of high side MOSFET.
LI 8 I Low-side driver control input TTL compatible thresholds. Unused inputs should be tied to ground and not left open.
LO 10 O Low-side gate driver output Connect to the gate of the low side MOSFET with a short low inductance path.
RT1 5 A High-side output edge delay programming Resistor from RT1 to ground programs the leading edge delay of the high side gate driver. The resistor should be placed close to the IC to minimize noise coupling from adjacent traces.
RT2 6 A Low-side output edge delay programming Resistor from RT2 to ground programs the leading edge delay of the low side gate driver. The resistor should be placed close to the IC to minimize noise coupling from adjacent traces.
VDD 1 P Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor, located as close to IC as possible.
VSS 9 G Ground return All signals are referenced to this ground.
(1) For the WSON package, it is recommended that the exposed pad on the bottom of the LM5100 and LM5101 be soldered to ground plane on the PC board, and the ground plane should extend out from beneath the IC to help dissipate the heat.
(2) P = Power, G = Ground, I = Input, O = Output, A = Analog