JAJSFD4A May   2018  – November 2018 LM5122ZA

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Lockout (UVLO)
      2. 8.3.2  High-Voltage VCC Regulator
      3. 8.3.3  Oscillator
      4. 8.3.4  Slope Compensation
      5. 8.3.5  Error Amplifier
      6. 8.3.6  PWM Comparator
      7. 8.3.7  Soft Start
      8. 8.3.8  HO and LO Drivers
      9. 8.3.9  Bypass Operation (VOUT = VIN)
      10. 8.3.10 Cycle-by-Cycle Current Limit
      11. 8.3.11 Clock Synchronization
      12. 8.3.12 Maximum Duty Cycle
      13. 8.3.13 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Control (Forced-PWM Mode and Diode-Emulation Mode)
      2. 8.4.2 MODE Control (Skip-Cycle Mode and Pulse-Skipping Mode)
      3. 8.4.3 Hiccup-Mode Overload Protection
      4. 8.4.4 Slave Mode and SYNCOUT
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Feedback Compensation
      2. 9.1.2 Sub-Harmonic Oscillation
      3. 9.1.3 Interleaved Boost Configuration
      4. 9.1.4 DCR Sensing
      5. 9.1.5 Output Overvoltage Protection
      6. 9.1.6 SEPIC Converter Simplified Schematic
      7. 9.1.7 Non-Isolated Synchronous Flyback Converter Simplified Schematic
      8. 9.1.8 Negative to Positive Conversion
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Timing Resistor RT
        2. 9.2.2.2  UVLO Divider RUV2, RUV1
        3. 9.2.2.3  Input Inductor LIN
        4. 9.2.2.4  Current Sense Resistor RS
        5. 9.2.2.5  Current Sense Filter RCSFP, RCSFN, CCS
        6. 9.2.2.6  Slope Compensation Resistor RSLOPE
        7. 9.2.2.7  Output Capacitor COUT
        8. 9.2.2.8  Input Capacitor CIN
        9. 9.2.2.9  VIN Filter RVIN, CVIN
        10. 9.2.2.10 Bootstrap Capacitor CBST and Boost Diode DBST
        11. 9.2.2.11 VCC Capacitor CVCC
        12. 9.2.2.12 Output Voltage Divider RFB1, RFB2
        13. 9.2.2.13 Soft-Start Capacitor CSS
        14. 9.2.2.14 Restart Capacitor CRES
        15. 9.2.2.15 Low-Side Power Switch QL
        16. 9.2.2.16 High-Side Power Switch QH and Additional Parallel Schottky Diode
        17. 9.2.2.17 Snubber Components
        18. 9.2.2.18 Loop Compensation Components CCOMP, RCOMP, CHF
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Slave Mode and SYNCOUT

The LM5122ZA is designed to easily implement dual (or higher) phase boost converters by configuring one controller as a master and all others as slaves. Slave mode is activated by connecting the FB pin to the VCC pin. The FB pin is sampled during initial power-on and if a slave configuration is detected, the state is latched. In the slave mode, the error amplifier is disabled and has a high impedance output, 10-μA hiccup-mode off-time charging current and 5-μA hiccup-mode off-time discharging current are disabled, 5-μA normal-state RES discharging current and 10-μA soft-start charging current are disabled, 30 μA fault-state RES charging current is changed to 35 μA. 10-μA UVLO hysteresis current source works the same as master mode. Also, in slave mode, the internal oscillator is disabled, and an external synchronization clock is required.

The SYNCOUT function provides a 180° phase shifted clock output, enabling easy dual-phase interleaved configuration. By directly connecting master1 SYNCOUT to slave1 SYNCIN, the switching frequency of slave controller is synchronized to the master controller with 180º phase shift. In master mode, if OPT pin is tied to GND, an internal oscillator clock divided by two with 50% duty cycle is provided to achieve an 180º phase-shifted operation in two phase interleaved configuration. Switching frequency of master controller is half of the external clock frequency with this configuration. If the OPT pin voltage is higher than 2.7-V OPT threshold or the pin is tied to VCC, SYNCOUT is disabled and the switching frequency of master controller becomes the same as the external clock frequency. An external synchronization clock should be always provided and directly connected to SYNCIN for master2, slave1 and slave2 configurations. See Interleaved Boost Configuration for detailed information.

Table 1. LM5122ZA Multiphase Configuration

MULTIPHASE CONFIGURATION FB OPT ERROR AMPLIFIER SWITCHING FREQUENCY SYNCOUT
Master1 Feedback GND Enable fSYNC/2, Free running with RT resistor fSYNC/2, fSW –180º
Slave1 VCC GND Disable fSYNC, No free running Disable
Master2 Feedback VCC Enable fSYNC, No free running Disable
Slave2 VCC VCC Disable fSYNC/2, No free running fSYNC/2, fSW –180º