JAJSJD3A June   2021  – June 2021 LM5146

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 12-A High-Efficiency Synchronous Buck DC/DC Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Custom Design With WEBENCH® Tools
        4. 9.2.1.4 Custom Design With Excel Quickstart Tool
        5. 9.2.1.5 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Telecom Power
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

EMI Filter Design

Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter output impedance must be less than the absolute value of the converter input impedance.

Equation 17. GUID-0BDBFA34-CE7F-4BD9-937A-B703463A0B64-low.gif

The EMI filter design steps are as follows:

  • Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the existing capacitance at the input of the switching converter.
  • Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a high current design.
  • Calculate input filter capacitor CF.
GUID-B9F51131-438C-47F0-8ACA-A56B21EAED47-low.gif Figure 9-4 Buck Regulator With π-Stage EMI Filter

By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to obtain the required attenuation as shown by Equation 18.

Equation 18. GUID-7F57066D-444A-4BEE-9F39-AF4AE99750CF-low.gif

where

  • VMAX is the noise specification in dBμV from the applicable EMI standard, for example CISPR 32 Class B
  • CIN is the existing input capacitance of the buck regulator
  • DMAX is the maximum duty cycle
  • IPEAK is the peak inductor current

For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI filter capacitance CF from Equation 19.

Equation 19. GUID-9A4FEFC4-8A5D-4FEE-B084-13C68C4482AB-low.gif

Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the filter is given by Equation 20.

Equation 20. GUID-9147F474-0D42-4BA7-8C46-9C38F8144948-low.gif

The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD must have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added damping is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LIN and CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 21.

Equation 21. GUID-B35BDE6E-18A5-42F8-A5DD-B50BE361C32E-low.gif

Select the damping resistor RD using Equation 22.

Equation 22. GUID-F53C67C3-1E14-4712-8816-A2619F652302-low.gif