The open-drain nFLT ouput directly follows the input signals of monitoring features. For instance if the power good flag triggers by V_o falling below the power good threshold the nFLT pins pulls low. After a power-cycle of the device or in case the internal failure signal disappears the nFLT pin will go back to HighZ. The input signals to the nFLT pin are digitally de-glitched. Due to this the maximum reaction time of the FLT pin is given by t_d(nFLT-PIN)

Figure 8-19 Functional Block Diagram nFLT-pin Logic

Thermal Shutdown (TSD)

To avoid the case of a thermal damage of the device the die temperature of the die is monitored. The device will stop operation once the sensed temperature rises over the thermal shutdown threshold. After the temperature drops below the thermal shutdown hysteresis the TSD signal goes back to normal and the converter will return to normal operation according to the main FSM definition.

Over Current or Short Circuit Protection

The device features a hiccup mode short circuit protection to avoid excessive power dissipation in the die or at the fault of the application in the System. The OCP triggers if the peak current sensing voltage between CSA-pin and CSB-pin is exceeded.

The protection feature will stop and restart the converter operation in case of a short is event is detected.

Output Over Voltage Protection 1 (OVP1)

This over voltage protection monitors the voltage of the FB-pin.

As this threshold is referenced to the V_(REF) the OVP1 continues its operation even if of tracking features has changed the V_o target value.

The converter maintains in regulation even the OVP1 threshold triggers.

The OVP1 is disabled during PSM to avoid additional leakage current. The OVP signal gets masked to avoid that a fault is indicated from this signal during the PSM operation.

This protection is disabled during the soft-start procedure.

Output Over Voltage protection 2 (OVP2)

This feature shall avoid any damage to the device in case the external feedback pin is not working properly i.e. is shorted to GND

If the output voltage threshold V_T+(OVP2) is reached on the VOUT-pin the buck-boost core logic disables the converter power stage and enters a high impedance state at the switch nodes. If the output voltage falls back under this threshold the convert operation is resumed.

Input Voltage Protection (IVP)

The input over voltage protection is part of the converter core modulation scheme. The IVP avoids any damage to the device in case the current flows from the output to the input and the input source can not sink current e.g. there is a diode in the supply path. If the converter forced PWM mode is active the current can go negative until the sink current limit. Once the input voltage threshold V_T+(IVP) is reach on the VIN-pin the protection disables the forced PWM mode and only allows current to flow from VIN to VOUT. After the input voltage drops under the input voltage protection threshold, the fPWM mode activates again.

Power Good

The device features a power good detection. The FB pin voltages gets contentiously monitors. If the sensed voltage drops below the PG falling threshold the signal is pulling low the nFLT pin.

This protection is disabled during the soft-start procedure.

Boot-strap Under Voltage Protection

The high side supply voltage for the gate driver are monitored by an UVLO comparator (BST_UV). This comparator monitors the differential voltage between SWx pin and HBx pin. If the measured voltage drops below V_{TH-(BST_UV)} the converter stops operation

Boot-strap Over Voltage Clamp

To protect the internal gate driver circuit the external FET gates and the internal circuit features an over voltage clamp. If the voltage goes above V_{TH(BST_OV)} the linear regulator sinks a current from HBx pin to SWx-pin as long as the voltage is above the threshold.