Figure 6-1 shows the circuit used to measure the GaN power FET switching parameters. The circuit is operated as a double-pulse tester. Consult external references for double-pulse tester details. The circuit operates in the boost configuration with the low-side LMG3622 being the device under test (DUT). The high-side LMG3622 acts as the double-pulse tester diode and circulates the inductor current in the off-state, third-quadrant conduction mode.

Figure 6-1 GaN Power FET Switching Parameters Test Circuit

Figure 6-2 shows the GaN power FET switching parameters.

The GaN power FET turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and turn-on rise time. Note that the turn-on rise time is the same as the V_DS 80% to 20% fall time. All three turn-on timing components are a function of the RDRV pin setting.

The GaN power FET turn-off transition has two timing components: turn-off delay time, and turn-off fall time. Note that the turn-off fall time is the same as the V_DS 20% to 80% rise time. The turn-off timing components are independent of the RDRV pin setting, but heavily dependent on the L_HB current.

The turn-on slew rate is measured over a smaller voltage delta (100 V) compared to the turn-on rise time voltage delta (240 V) to obtain a faster slew rate which is useful for EMI design. The RDRV pin is used to program the slew rate.

Figure 6-2 GaN Power FET Switching Parameters