SNLS233O April 2007 – July 2015 LMH0344
PRODUCTION DATA.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH0344 is a single channel 3 Gbps HD – SD SDI Adaptive Cable Equalizer designed to equalize data transmitted over cable or any media with similar dispersive loss characteristics. The equalizer operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, and ST 259. Additional features include separate carrier detect and output mute pins which may be tied together to mute the output when no signal is present. A programmable mute reference is provided to mute the output at a selectable level of signal degradation. The bypass pin allows the adaptive equalizer to be bypassed.
The LMH0344 accepts either a differential or single-ended input. The input must be AC-coupled. The LMH0344 correctly handles equalizer pathological signals for standard definition and high definition serial digital video, as described in RP 178 and RP 198, respectively.
8.2 Typical Application
Figure 3. Typical 2.97-Gbps SDI De-Serializer Application
8.2.1 Design Requirements
Table 1 lists the design parameters for the LMH0344.
Table 1. LMH0344 Design Parameters
| DESIGN PARAMETER | REQUIREMENT |
|---|---|
| Input AC-coupling capacitors | Required. A common type of AC-coupling capacitor is 1 µF ±10% X7R ceramic capacitor (0402 or 0201 size). Capacitors may be implemented on the PCB or in the connector. |
| Output AC-coupling capacitors | The user should check input common mode voltage of the device attached to SDO . If AC-coupling Capacitor is required, AC-coupling capacitor is expected to be 4.7 µF ±10%. |
| Input launch amplitude | Refer to DC Electrical Characteristics and AC Electrical Characteristics. |
8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
- Maximum power draw for PCB regulator selection. Use maximum power consumption in the data sheet.
- Closely compare schematic against typical connection diagram in the data sheet.
- Plan out the PCB layout and component placement to minimize parasitic losses and reflections.
- To optimize return loss result, return loss components may need to be adjusted.
8.2.3 Application Curves
Figure 4 and Figure 5 depict the differential output eye diagrams for SDO and SDO at 2.97 Gbps using B1694A cable.
Figure 4. Serial Data Output After Equalizing 100m of Belden 1694A 2.97-Gbps PRBS10
Figure 5. Serial Data Output After Equalizing 10m of Belden 1694A 2.97-Gbps PRBS10
8.3 Dos and Don'ts
Pay special attention to the PCB layout for the high speed signals. The SMPTE organization specifies the requirements for the Serial Digital Interface to transport digital video at SD, HD, and 3 Gbps data rates over coaxial cables. One of the requirements is meeting the required Return Loss. This requirement specifies how closely the port resembles 75-Ω impedance across a specified frequency band. The SMPTE specifications also defines the use of AC-coupling capacitors for transporting uncompressed serial data streams with heavy low frequency content. This specification requires the use of a 1 µF, AC-coupling capacitors on the input of the LMH0344 to avoid low frequency DC wander.