SNOSB47E May   2011  – August 2016 LMH6521

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Characteristics
      2. 7.3.2 Output Characteristics
      3. 7.3.3 Output Connections
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Digital Control
      2. 7.5.2 Parallel Mode (MOD1 = 1, MOD0 = 1)
      3. 7.5.3 Serial Mode: SPI Compatible Interface (MOD1 = 1, MOD0 = 0)
      4. 7.5.4 Pulse Mode (MOD1 = 0, MOD0 = 1)
      5. 7.5.5 Interface to ADC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Layout for the LMH6521 is critical to achieve specified performance. Circuit symmetry is necessary for good HD2 performance. Input traces must be 200-Ω impedance transmission lines. To reduce output to input coupling, use ground plane fill between the amplifier input and output traces as shown in Figure 42. The output inductors contribute to crosstalk if placed too closely together. See Figure 42 for recommended placement of the output bias inductors. Output termination resistors and coupling capacitors must be placed as closely to the output inductors as possible.

10.2 Layout Example

LMH6521 layout_example_snosb47e.gif Figure 42. LMH6521 Layout Example

10.3 Thermal Considerations

The LMH6521 is packaged in a thermally enhanced WQFN package and features an exposed pad that is connected to the GND pins. TI recommends attaching the exposed pad directly to a large power supply ground plane for maximum heat dissipation. The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered down to a thermal land on the PCB board with the through vias planted underneath the thermal land. The thermal land can be connected to any ground plane within the PCB. However, it is also very important to maintain good high-speed layout practices when designing a system board.

The LMH6521EVAL evaluation board implemented an eight metal layer PCB with (a) 4 oz. copper inner ground planes (b) additonal through vias and (c) maximum bottom layer metal coverage to assist with device heat dissipation. These PCB design techniques assist with the heat dissipation of the LMH6521 to optimize distortion performance. See AN–2045 LMH6521EVAL Evaluation Board (SNOA551) for suggested layout techniques.