SNOSC72F June   2012  – February 2015 LMH6881

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Single-Ended Input
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Digital Control of the Gain and Power-Down Pins
        1. 7.5.1.1 Parallel Interface
        2. 7.5.1.2 SPI-Compatible Serial Interface
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Characteristics
      2. 8.1.2 Output Characteristics
      3. 8.1.3 Interfacing to an ADC
        1. 8.1.3.1 ADC Noise Filter
        2. 8.1.3.2 AC Coupling to ADC
        3. 8.1.3.3 DC Coupling to ADC
      4. 8.1.4 Figure of Merit: Dynamic Range Figure
    2. 8.2 Typical Applications
      1. 8.2.1 LMH6881 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LMH6881 Used as Twisted-Pair Cable Driver
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Uncontrolled Impedance Traces
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT
Positive Supply Voltage (VCC) −0.6 5.5 V
Differential Voltage between Any Two Grounds < 200 mV
Analog Input Voltage Range −0.6 5.5 V
Digital Input Voltage Range −0.6 5.5 V
Output Short Circuit Duration (one pin to ground) Infinite
Junction Temperature 150 °C
Soldering Information Infrared or Convection (30 sec) 260 °C
Storage temperature range, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage (VCC) 4.75 5.25 V
Differential Voltage Between Any Two Grounds < 10 mV
Analog Input Voltage Range, AC Coupled 0 VCC V
Temperature Range(1) −40 85 °C
(1) The maximum power dissipation is a function of TJ(MAX), θJA and the ambient temperature TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.

6.4 Thermal Information

THERMAL METRIC(1) LMH6881 UNIT
RTW (WQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 38.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.9
RθJB Junction-to-board thermal resistance 16.7
ψJT Junction-to-top characterization parameter 0.5
ψJB Junction-to-board characterization parameter 16.8
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics(1)(4)(5)

The following specifications apply for single supply with VCC = 5 V, Maximum Gain (26 dB), RL = 200 Ω, fin = 100 MHz.
TEST CONDITIONS MIN(3) TYP(2) MAX(3) UNIT
DYNAMIC PERFORMANCE
3 dBBW −3-dB Bandwidth VOUT= 2 VPPD 2.4 GHz
NF Noise Figure Source Resistance (Rs) = 100 Ω 9.7 dB
OIP3 Output Third Order Intercept Point(7) f = 100 MHz, POUT = 4 dBm per tone, tone spacing = 1 MHz 44 dBm
f = 200 MHz, POUT = 4 dBm per tone, tone spacing = 2 MHz 42
OIP2 Output Second Order Intercept Point POUT= 4 dBm per Tone, f1 =112.5 MHz, f2 = 187.5 MHz 76 dBm
IMD3 Third Order Intermodulation Products f = 100 MHz, POUT = 4 dBm per tone, tone spacing = 1 MHz −80 dBc
f = 200 MHz, POUT = 4 dBm per tone, tone spacing =2 MHz −76
P1dB 1dB Compression Point Output Power 17 dBm
HD2 Second Order Harmonic Distortion f = 200 MHz, POUT = 4 dBm −70 dBc
HD3 Third Order Harmonic Distortion f = 200 MHz, POUT = 4 dBm −76 dBc
CMRR Common Mode Rejection Ratio(6) Pin = −15 dBm, f = 100 MHz −40 dBc
SR Slew Rate 6000 V/us
Output Voltage Noise Maximum Gain f > 1 MHz 47 nV/√Hz
Input Referred Voltage Noise Maximum Gain f > 1 MHz 2.3 nV/√Hz
ANALOG I/O
RIN Input Resistance Differential, INPD to INMD 100 Ω
RIN Input Resistance Single Ended, INPS or INPD, 50-Ω termination on unused input 50 Ω
VICM Input Common Mode Voltage Self Biased 2.5 V
Maximum Input Voltage Swing Volts peak to peak, differential 2.85 VPPD
Maximum Differential Output Voltage Swing Differential, f < 10 MHz 6 VPPD
ROUT Output Resistance Differential, f = 100 MHz 0.4 Ω
GAIN PARAMETERS
Maximum Voltage Gain Parallel Inputs (INPD and INMD), Rs = 100 Ω 26 dB
Single-ended input (INMS or INPS), 50-Ω Rs and 50-Ω termination on unused input. 26.6
Minimum Gain Parallel Inputs, Rs = 100 Ω 6 dB
Gain Steps Available using SPI interface 80
Available using parallel interface 10
Gain Step Size Available using SPI interface 0.25 dB
Available using parallel interface 2
Gain Step Error Any two adjacent steps over entire range ±0.125 dB
Gain Step Phase Shift Any two adjacent steps over entire range ±3 Degrees
Gain Step Switching Time 20 ns
Enable/ Disable Time Settled to 90% level 15 ns
POWER REQUIREMENTS
ICC Supply Current 100 135 mA
P Power 0.5 W
ICCD Disabled Supply Current 15 mA
ALL DIGITAL INPUTS
Logic Compatibility TTL, 2.5-V CMOS, 3.3-V CMOS, 5-V CMOS
VIL Logic Input Low Voltage 0.4 V
VIH Logic Input High Voltage 2.0 - 5.0 V
IIH Logic Input High Input Current −9 μA
IIL Logic Input Low Input Current −47 μA
PARALLEL MODE TIMING
tGS Setup Time 3 ns
tGH Hold Time 3 ns
SERIAL MODE
fCLK SPI Clock Frequency 50% duty cycle 10 50 MHz
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No verification of parametric performance is indicated in the electrical tables under conditions different than those tested
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(3) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods.
(4) Negative input current implies current flowing out of the device.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) CMRR is defined as the differential response at the output in response to a common mode signal at the input.
(7) OIP3 is the third order intermodulation intercept point. In this data sheet OIP3 numbers are single power measurements where OIP3 = IMD3 / 2 + POUT (per tone). OIP2 is the second order intercept point where OIP2 = IMD2 + POUT (per tone). HD2 is the second order harmonic distortion and is a single tone measurement. HD3 is the third order harmonic distortion and is a single tone measurement. Power measurements are made at the amplifier output pins.

6.6 Typical Characteristics

(Unless otherwise specified, the following conditions apply: TA = 25°C, VCC = 5 V, RL = 200 Ω, Maximum Gain, Differential Input). LMH6882 devices have been used for some typical performance plots.

30195887.gifFigure 1. Frequency Response over Gain Range, 4-dB Steps
30195861.gifFigure 3. OIP3 vs Output Power
30195856.gifFigure 5. OIP3 vs Frequency
30195873.gifFigure 7. OIP3 vs Temperature
30195858.gifFigure 9. Supply Current vs Temperature
d1_snosc72.gif
Pout = 4 dBm
Figure 11. HD2 vs Frequency
HD23_SNOSC72E.pngFigure 13. HD2 and HD3 vs Voltage Gain
30195821.gifFigure 15. HD3 vs Output Power
30195836.gifFigure 17. Gain Step Amplitude Error
30195837.gifFigure 19. Cumulative Amplitude Error
30195850.gifFigure 21. Noise Figure vs Voltage Gain
30195848.gifFigure 23. Channel Enable Control Timing Behavior
30195843.gifFigure 25. 8-dB Step Control Timing Behavior
30195875.gifFigure 27. Input Impedance
30195853.gifFigure 29. OIP3 Overvoltage Gain Range
30195853.gifFigure 2. OIP3 vs Voltage Gain
30195867.gifFigure 4. Dynamic Range Figure vs Voltage Gain
30195855.gifFigure 6. OIP3 vs Supply Voltage
30195893.gifFigure 8. OIP2 vs Voltage Gain
30195859.gifFigure 10. Maximum Voltage Gain vs Temperature
d2_snosc72.gif
Pout = 4 dBm
Figure 12. HD3 vs Frequency
30195820.gifFigure 14. HD2 vs Output Power
30195885.gifFigure 16. Output Power vs Input Power
30195839.gifFigure 18. Gain Step Phase Error
30195838.gifFigure 20. Cumulative Phase Error
30195851.gifFigure 22. Noise Figure vs Frequency
30195842.gifFigure 24. 16-dB Gain Control Timing Behavior
30195841.gifFigure 26. Common Mode Rejection (Sdc21) vs Frequency
30195876.gifFigure 28. Output Impedance
30195896.gifFigure 30. Noise Figure Overvoltage Gain Range DVGA Response Shown for Comparison

6.6.1 Single-Ended Input

(Unless otherwise specified, the following conditions apply: TA = 25°C, VCC = 5 V, RL = 200 Ω, Maximum Gain.)

30195846.gifFigure 31. OIP3 vs Voltage Gain
fig33_snosc72.gif
Pout = 4 dBm
Figure 33. HD3 vs Frequency
30195845.gifFigure 35. Noise Figure vs Voltage Gain
fig32_snosc72.gif
Pout = 4 dBm
Figure 32. HD2 vs Frequency
d3_snosc72.gif
f = 100 MHz Pout = 4 dBm
Figure 34. HD2 and HD3 vs Voltage Gain
30195888.gifFigure 36. Single-Ended Input Impedance