JAJSPW5C November   2023  – May 2024 LMKDB1108 , LMKDB1120

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
        5. 8.3.4.5 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLOCK INPUT REQUIREMENTS
VIN, cross Clock input crossing point voltage 100 1400 mV
DCIN Clock input duty cycle 45 55 %
VIN Differential clock input amplitude (half of differential peak-peak voltage) f0 ≤ 300 MHz 200 2000 mV
300 MHz < f0 ≤ 400 MHz 250 2000 mV
dVIN/dt Clock input slew rate Measured from –150 mV to +150 mV on the differential waveform 0.6 V/ns
CLOCK OUTPUT CHARACTERISTICS - 100 MHz 85 Ω PCIe
VOH,AC Output voltage high DB2000QL AC test load(6) 670 820 mV
VOL,AC Output voltage low –100 100 mV
Vmax,AC Output max voltage (including overshoot) 670 920 mV
Vmin,AC Output min voltage (including undershoot) –100 100 mV
VOH,DC Output voltage high with DC test load DB2000QL DC test load(2) 225 270 mV
VOL,DC Output voltage low with DC test load 10 150 mV
Vovs,DC Output overshoot voltage with DC test load 75 mV
Vuds,DC Output undershoot voltage with DC test load –75 mV
Zdiff Differential output impedance Measured at VOL/VOH, VDD = 3.3 V 80.75 85 89.25 Ω
Measured at VOL/VOH, VDD = 1.8 V 81 85 90 Ω
Zdiff-crossing Differential output impedance - crossing Measured during transition 68 85 102 Ω
dV/dt Output slew rate Measured from –150 mV to +150 mV on the differential waveform. Lowest slew rate(6)(7) 1.5 2.2 V/ns
Measured from –150 mV to +150 mV on the differential waveform. Low slew rate(6)(7) 1.8 2.6 V/ns
Measured from –150 mV to +150 mV on the differential waveform. High slew rate (default)(6)(7) 2 2.9 V/ns
Measured from –150 mV to +150 mV on the differential waveform. Highest slew rate(6)(7) 2.4 4 V/ns
∆dV/dt Rising edge rate to falling edge rate matching DB2000QL AC test load(6) 10 %
DCD Duty cycle distortion Measured on the differential waveform. Input duty cycle = 50%(6) –1 1 %
Vcross,AC Absolute crossing point voltage DB2000QL AC test load(6) 250 550 mV
Vcross,DC Absolute crossing point voltage DB2000QL DC test load(2) 130 200 mV
∆Vcross,AC Variation of Vcross over all clock edges DB2000QL AC test load(6) 140 mV
∆Vcross-DC Variation of Vcross over all clock edges DB2000QL DC test load(2) 35 mV
|VRB| Absolute value of ring back voltage as defined in PCIe DB2000QL AC test load(6) 100 mV
tstable Time before VRB is allowed DB2000QL AC test load(6) 500 ps
CLOCK OUTPUT CHARACTERISTICS - 100 MHz 100 Ω PCIe
Vmax Output voltage high including overshoot PCIe AC test load(1) 670 920 mV
Vmin Output voltage low including undershoot PCIe AC test load(1) –100 100 mV
VOH Output voltage high PCIe AC test load(1) 670 820 mV
VOL Output voltage low PCIe AC test load(1) –100 100 mV
Zdiff Differential output DC impedance VDD = 3.3 V 95 100 105 Ω
VDD = 1.8 V 95 100 105 Ω
dV/dt Output slew rate Measured from –150 mV to +150 mV on the differential waveform. Lowest slew rate(1)(7) 1.5 2.2 V/ns
Measured from –150 mV to +150 mV on the differential waveform. Low slew rate(1)(7) 1.8 2.6 V/ns
Measured from –150 mV to +150 mV on the differential waveform. High slew rate(1)(7) 2 2.9 V/ns
Measured from –150 mV to +150 mV on the differential waveform. Highest slew rate(1)(7) 2.4 4 V/ns
∆dV/dt Rising edge rate to falling edge rate matching PCIe AC test load(1) 10 %
DCD Duty cycle distortion Measured on the differential waveform. Input duty cycle = 50%(1) –1 1 %
Vcross Absolute crossing point voltage PCIe AC test load(1) 250 550 mV
∆Vcross Variation of Vcross over all clock edges PCIe AC test load(1) 140 mV
|VRB| Absolute value of ring back voltage as defined in PCIe PCIe AC test load(1) 100 mV
tstable Time before VRB is allowed PCIe AC test load(1) 500 ps
CLOCK OUTPUT CHARACTERISTICS - non-PCIe
VOH Output voltage high Output swing programmed to 800 mV. f0 = 156.25 MHz or 312.5 MHz 720 880 mV
VOL Output voltage low –120 120 mV
VOH Output voltage high Output swing programmed to 900 mV. f0 = 156.25 MHz or 312.5 MHz 780 980 mV
VOL Output voltage low –120 120 mV
tR, tF Rise/fall time on single-ended waveform, 20% to 80% Output swing programmed to 800 mV. Fastest slew rate. f0 = 156.25 MHz or 312.5 MHz 340 ps
Output swing programmed to 900 mV. Fastest slew rate. f0 = 156.25 MHz or 312.5 MHz 370 ps
DCD Duty cycle distortion Input duty cycle = 50% –1 1 %
SKEW AND DELAY CHARACTERISTICS
tskew Output-to-output skew Same bank 50 ps
Regardless of banks 50 ps
Part-to-part skew 330 ps
tPD Input-to-output delay 1 ns
ΔtPD Input-to-output delay variation Single device over temperature and voltage 1.7 ps/℃
FREQUENCY AND TIMING CHARACTERISTICS
f0 Operating frequency Automatic Output Disable functionality is disabled 1 400 MHz
Automatic Output Disable functionality is enabled 25 400 MHz
tstartup Startup time Cold start. Measured from VDD valid (90% of final VDD) to output clock stable(3). Input clock is provided before VDD is valid. PWRGD_PWRDN# pin is tied to VDD. f0 ≥ 100 MHz 0.4 ms
Cold start. Measured from VDD valid (90% of final VDD) to output clock stable(3). Input clock is provided before VDD is valid. PWRGD_PWRDN# pin is tied to VDD. f0 < 100 MHz 0.8 ms
tstable Clock stabilization time VDD is stable. Measured from PWRGD assertion(4) to output clock stable. f0 ≥ 100 MHz(3) 0.4 ms
VDD is stable. Measured from PWRGD assertion(4) to output clock stable. f0 < 100 MHz(3) 0.8 ms
tPD# Powerdown deassertion time Measured from PWRDN# deassertion(4) to output clock stable. f0 ≥ 100 MHz(3) 0.15 ms
Measured from PWRDN# deassertion(4) to output clock stable. f0 < 100 MHz(3) 0.5 ms
tOE Output enable/disable time Time elapsed from OE assertion/deassertion(4) to output clock starts/stops 4 10 clk
tLOS-assert LOS# assertion time Time elapsed from loss of input clock to LOS# assertion. f0 < 100 MHz 120 ns
Time elapsed from loss of input clock to LOS# assertion. f0 ≥ 100 MHz 120 ns
tLOS-deassert LOS# deassertion time Time elapsed from presence of input clock to LOS# deassertion. f0 < 100 MHz 340 ns
Time elapsed from presence of input clock to LOS# deassertion. f0 ≥ 100 MHz 105 ns
tAOD Automatic output disable time Time elapsed from LOS# assertion to output disable (both outputs are low/low). f0 < 100 MHz 0.07 ns
Time elapsed from LOS# assertion to output disable (both outputs are low/low), f0 ≥ 100 MHz 0.07 ns
tAOE Automatic output enable time Time elapsed from LOS# deassertion to output clock stable. f0 < 100 MHz(3) 115 ns
Time elapsed from LOS# deassertion to output clock stable, f0 ≥ 100 MHz(3) 22 ns
tswitch Switch time Switch between two 100MHz input clocks (MUX only) 70 ns
JITTER CHARACTERISTICS
JPCIe1-CC PCIe Gen 1 CC jitter Single clock input. Input slew rate ≥ 3.5 V/ns. Differential input swing ≥ 1600 mV 442.5 fs
JPCIe2-CC PCIe Gen 2 CC jitter 39 fs
JPCIe3-CC PCIe Gen 3 CC jitter 12.3 fs
JPCIe4-CC PCIe Gen 4 CC jitter 12.3 fs
JPCIe5-CC PCIe Gen 5 CC jitter 4.9 fs
JPCIe6-CC PCIe Gen 6 CC jitter 3 fs
JPCIe2-IR PCIe Gen 2 IR jitter 33.8 fs
JPCIe3-IR PCIe Gen 3 IR jitter 14.1 fs
JPCIe4-IR PCIe Gen 4 IR jitter 14.5 fs
JPCIe5-IR PCIe Gen 5 IR jitter 3.9 fs
JPCIe6-IR PCIe Gen 6 IR jitter 3 fs
JPCIe1-CC PCIe Gen 1 CC jitter Single clock input. Input slew rate ≥ 1.5 V/ns. Differential input swing ≥ 800 mV 583.2 fs
JPCIe2-CC PCIe Gen 2 CC jitter 51.3 fs
JPCIe3-CC PCIe Gen 3 CC jitter 16 fs
JPCIe4-CC PCIe Gen 4 CC jitter 16 fs
JPCIe5-CC PCIe Gen 5 CC jitter 6.4 fs
JPCIe6-CC PCIe Gen 6 CC jitter 3.9 fs
JPCIe2-IR PCIe Gen 2 IR jitter 41.9 fs
JPCIe3-IR PCIe Gen 3 IR jitter 18.3 fs
JPCIe4-IR PCIe Gen 4 IR jitter 18.9 fs
JPCIe5-IR PCIe Gen 5 IR jitter 5.1 fs
JPCIe6-IR PCIe Gen 6 IR jitter 3.8 fs
JPCIe1-CC PCIe Gen 1 CC jitter Both inputs (for MUX only) have running clocks. CLK_SEL pin = low (CLKIN0 = 100MHz,  CLKIN1 = 99.75MHz), mid (CLKIN0 = 100MHz,  CLKIN1 = 99.75MHz) or high (CLKIN0 = 99.7MHz,  CLKIN1 = 100MHz). Input slew rate ≥ 3.5 V/ns. Differential input swing ≥ 1600 mV 255.3 517.5 fs
JPCIe2-CC PCIe Gen 2 CC jitter 30 45.3 fs
JPCIe3-CC PCIe Gen 3 CC jitter 8.3 13.7 fs
JPCIe4-CC PCIe Gen 4 CC jitter 8.3 13.7 fs
JPCIe5-CC PCIe Gen 5 CC jitter 2.9 5.5 fs
JPCIe6-CC PCIe Gen 6 CC jitter 2 3.5 fs
JPCIe2-IR PCIe Gen 2 IR jitter 31.9 48.5 fs
JPCIe3-IR PCIe Gen 3 IR jitter 8.8 21.7 fs
JPCIe4-IR PCIe Gen 4 IR jitter 8.8 21.7 fs
JPCIe5-IR PCIe Gen 5 IR jitter 3.4 6.7 fs
JPCIe6-IR PCIe Gen 6 IR jitter 2.8 4.7 fs
JPCIe1-CC PCIe Gen 1 CC jitter Both inputs (for MUX only) have running clocks. CLK_SEL pin = low (CLKIN0 = 100MHz,  CLKIN1 = 99.75MHz), mid (CLKIN0 = 100MHz,  CLKIN1 = 99.75MHz) or high (CLKIN0 = 99.7MHz,  CLKIN1 = 100MHz). Crosstalk included. Input slew rate ≥ 1.5 V/ns. Differential input swing ≥ 800 mV 388.6 669.5 fs
JPCIe2-CC PCIe Gen 2 CC jitter 35.4 57 fs
JPCIe3-CC PCIe Gen 3 CC jitter 10.1 17.1 fs
JPCIe4-CC PCIe Gen 4 CC jitter 10.1 17.1 fs
JPCIe5-CC PCIe Gen 5 CC jitter 3.7 7.4 fs
JPCIe6-CC PCIe Gen 6 CC jitter 2.4 4.4 fs
JPCIe2-IR PCIe Gen 2 IR jitter 35.4 57 fs
JPCIe3-IR PCIe Gen 3 IR jitter 9.8 24 fs
JPCIe4-IR PCIe Gen 4 IR jitter 9.9 24 fs
JPCIe5-IR PCIe Gen 5 IR jitter 4.3 8.6 fs
JPCIe6-IR PCIe Gen 6 IR jitter 3.3 6 fs
JDB2000QL DB2000QL filter Input slew rate ≥ 1.5 V/ns. Differential input swing ≥ 800 mV(6) 8.7 11.5 fs
Input slew rate ≥ 3.5 V/ns. Differential input swing ≥ 1600 mV(6) 6.5 9 fs
JRMS-additive Additive 12 kHz to 20 MHz RMS jitter f = 100 MHz, slew rate ≥ 3.5 V/ns 27.3 37.5 fs
f = 100 MHz, slew rate ≥ 1.5 V/ns 37.4 48.5 fs
Additive 12 kHz to 20 MHz RMS jitter f = 156.25 MHz, slew rate ≥ 3.5 V/ns 21.9 31 fs
f = 156.25 MHz, slew rate ≥ 1.5 V/ns 29.4 38.5 fs
Additive 12 kHz to 70 MHz RMS jitter f = 156.25 MHz, slew rate ≥ 3.5 V/ns 35.1 48.5 fs
f = 156.25 MHz, slew rate ≥ 1.5 V/ns 47.1 60.5 fs
Additive 12 kHz to 20 MHz RMS jitter f = 312.5 MHz, slew rate ≥ 3.5 V/ns 19.3 28 fs
f = 312.5 MHz, slew rate ≥ 1.5 V/ns 27.4 39.5 fs
Additive 12 kHz to 70 MHz RMS jitter f = 312.5 MHz, slew rate ≥ 3.5 V/ns 29.5 41.5 fs
f = 312.5 MHz, slew rate ≥ 1.5 V/ns 40.7 58 fs
SUPPLY CURRENT CHARACTERISTICS
IDD,total LMKDB1204 total supply current All outputs running, f0 = 100 MHz 54 mA
IDD,total LMKDB1108 total supply current All outputs running, f0 = 100 MHz 85.7 mA
IDD,total LMKDB1120 total supply current All outputs running, f0 = 100 MHz 162 mA
IDD,core LMKDB1204 core supply current Pin PWRGD/PWRDN# = high, all outputs disabled 25.5 mA
IDD,core LMKDB1108 core supply current Pin PWRGD/PWRDN# = high, all outputs disabled 36.3 mA
IDD,core LMKDB1120 core supply current Pin PWRGD/PWRDN# = high, all outputs disabled 37.9 mA
IDDO Output supply current per output f0 = 100 MHz 6.4 mA
f0 = 400 MHz 9.2 mA
IPD LMKDB1204 power down current Pin PWRGD/PWRDN# = low 5.6 mA
IPD LMKDB1108 or LMKDB1120 power down current Pin PWRGD/PWRDN# = low 5.6 mA
PSNR CHARACTERISTICS
PSNR Power Supply Noise Rejection, VDD = 3.3 V(5) 10 kHz noise ripple –93 dBc
50 kHz noise ripple –91 dBc
100 kHz noise ripple –91 dBc
500 kHz noise ripple –95 dBc
1 MHz noise ripple –96 dBc
5 MHz noise ripple –111 dBc
10 MHz noise ripple –99 dBc
Power Supply Noise Rejection, VDD = 1.8 V(5) 10 kHz noise ripple –85 dBc
50 kHz noise ripple –89 dBc
100 kHz noise ripple –91 dBc
500 kHz noise ripple –93 dBc
1 MHz noise ripple –94 dBc
5 MHz noise ripple –109 dBc
10 MHz noise ripple –97 dBc
I/O CHARACTERISTICS
VIH Input voltage high 2-level logic input, VDD = 3.3 V ± 10% 2 VDD + 0.3 V
VIL Input voltage low –0.3 0.8 V
VIH Input voltage high 3-level logic input, VDD = 3.3 V ± 10% 2.4 VDD + 0.3 V
VIM Input voltage mid 1.2 1.8 V
VIL Input voltage low –0.3 0.8 V
VIH Input voltage high 2-level logic input, VDD = 1.8 V ± 5% 1.3 VDD + 0.3 V
VIL Input voltage low –0.3 0.4 V
VIH Input voltage high 3-level logic input, VDD = 1.8 V ± 5% 1.3 VDD + 0.3 V
VIM Input voltage mid 0.65 0.95 V
VIL Input voltage low –0.3 0.4 V
VOH Output high voltage SBI_OUT, IOH = -2 mA 2.4 VDD + 0.3 V
VOL Output low voltage SBI_OUT, IOL = 2 mA 0.4 V
IIN Input leakage current CLKINx_P –40 40 µA
CLKINx_N –40 40 µA
single-ended inputs with internal pulldown –30 30 µA
single-ended inputs without internal pulldown –5 5 µA
3-level logic input –30 30 µA
RPU,PD Internal pullup/pulldown resistor for single-ended inputs 120 kΩ
SMBUS ELECTRICAL CHARACTERISTICS
VIH SMB_CLK, SMB_DATA input high voltage 0.8 × VDD V
VIL SMB_CLK, SMB_DATA input low voltage 0.3 × VDD V
VHYS Hysteresis of Schmitt Trigger Inputs 0.05 × VDD V
VOL SMB_DATA output low voltage IOL = 4 mA 0.4 V
ILEAK SMB_CLK, SMB_DATA input leakage –10 10 µA
CPIN SMB_CLK, SMB_DATA pin capacitance 10 pF
(1) PCIe AC test load
(2) DB2000QL DC test load
(3) First clock edge is used for timing measurements. Clock outputs are muted until stabilized.
(4) For input pins, assertion or deassertion starts when the input voltage reaches the minimum voltage required for a "high" level, or the maximum voltage required for a "low" level
(5) All power supply pins are tied together. A 0.1µF capacitor is placed close to each power supply pin. 50 mVpp ripple is applied before the decoupling capacitors. Measure the spur level at the clock output
(6) DB2000QL AC test load
(7) Slew rate is highly dependent on PCB trace characteristics