JAJSAM4D September   2007  – August 2016 LMV641

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics: 2.7 V
    6. 6.6 DC Electrical Characteristics: 10 V
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Voltage and Low-Power Operation
      2. 7.3.2 Wide Bandwidth
      3. 7.3.3 Low Input Referred Noise
      4. 7.3.4 Ground Sensing and Rail-to-Rail Output
      5. 7.3.5 Small Size
    4. 7.4 Device Functional Modes
      1. 7.4.1 Stability of Op Amp Circuits
        1. 7.4.1.1 In The Loop Compensation
        2. 7.4.1.2 Compensation by External Resistor
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Gain, Low-Power Inverting Amplifiers
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Anisotropic Magnetoresistive Sensor
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Gain Error and Bandwidth Consideration if Using an Analog to Digital Converter
      3. 8.2.3 Voiceband Filter
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The LMV641 is a wide-bandwidth, low-power operational amplifier with an extended power supply voltage range of 2.7 V to 12 V. The device is unity-gain stable with a 10 MHz of gain bandwidth product. Operating on a typical supply current of 138 µA, it provides a PSRR of 105 dB, CMRR of 120 dB, VOS of 500 µV, input referred voltage noise of 14 nV/√Hz, and a THD of 0.002%. This amplifier has a rail-to-rail output stage and a common mode input voltage which includes the negative supply.

7.2 Functional Block Diagram

LMV641 Op_Amp_Triangle_Block_Diagram.gif

7.3 Feature Description

7.3.1 Low-Voltage and Low-Power Operation

The LMV641 has performance guaranteed at supply voltages of 2.7 V and 10 V. It is ensured to be operational at all supply voltages between 2.7 V and 12 V. The LMV641 draws a low supply current of 138 µA. The LMV641 provides the low-voltage and low-power amplification, which is essential for portable applications.

7.3.2 Wide Bandwidth

Despite drawing the very low supply current of 138 µA, the LMV641 manages to provide a wide unity gain bandwidth of 10 MHz. This is easily one of the best bandwidth to power ratios ever achieved, and allows this op amp to provide wideband amplification while using the minimum amount of power. This makes the LMV641 ideal for low power signal processing applications such as portable media players and other accessories.

7.3.3 Low Input Referred Noise

The LMV641 provides a flatband input referred voltage noise density of 14 nV/Hz, which is significantly better than the noise performance expected from a low-power op amp. This op amp also feature exceptionally low 1/f noise, with a very low 1/f noise corner frequency of 4 Hz. Because of this the LMV641 is ideal for low-power applications which require decent noise performance, such as PDAs and portable sensors.

7.3.4 Ground Sensing and Rail-to-Rail Output

The LMV641 has a rail-to-rail output stage, which provides the maximum possible output dynamic range. This is especially important for applications requiring a large output swing. The input common mode range of this part includes the negative supply rail which allows direct sensing at ground in a single supply operation.

7.3.5 Small Size

The small footprint of the packages for the LMV641 saves space on printed-circuit boards, and enables the design of smaller and more compact electronic products. Long traces between the signal source and the op amp make the signal path susceptible to noise. By using a physically smaller package, these op amps can be placed closer to the signal source, reducing noise pickup and enhancing signal integrity.

7.4 Device Functional Modes

7.4.1 Stability of Op Amp Circuits

If the phase margin of the LMV641 is plotted with respect to the capacitive load (CL) at its output, and if CL is increased beyond 100 pF then the phase margin reduces significantly. This is because the op amp is designed to provide the maximum bandwidth possible for a low supply current. Stabilizing the LMV641 for higher capacitive loads would have required either a drastic increase in supply current, or a large internal compensation capacitance, which would have reduced the bandwidth. Hence, if this device is to be used for driving higher capacitive loads, it will have to be externally compensated.

LMV641 20203359.gif Figure 36. Gain vs Frequency for an Op Amp

An op amp, ideally, has a dominant pole close to DC which causes its gain to decay at the rate of 20 dB/decade with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until the op amp's unity gain bandwidth, then the op amp is stable. If, however, a large capacitance is added to the output of the op amp, it combines with the output impedance of the op amp to create another pole in its frequency response before its unity gain frequency (Figure 36). This increases the ROC to 40 dB/decade and causes instability.

In such a case, a number of techniques can be used to restore stability to the circuit. The idea behind all these schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which ensures stability.

7.4.1.1 In The Loop Compensation

Figure 37 illustrates a compensation technique, known as in the loop compensation, that employs an RC feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF, is inserted across the feedback resistor to bypass CL at higher frequencies.

LMV641 20203358.gif Figure 37. In the Loop Compensation

The values for RS and CF are decided by ensuring that the zero attributed to CF lies at the same frequency as the pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for by the presence of the zero, and that the ROC is maintained at 20 dB/ decade. For the circuit shown in Figure 37 the values of RS and CF are given by Equation 1. Values of RS and CF required for maintaining stability for different values of CL, as well as the phase margins obtained, are shown in Table 1. RF and RIN are 10 kΩ, RL is 2 kΩ, while ROUT is 680Ω.

Equation 1. LMV641 20203338.gif

Table 1. Loop Compensation Stability

CL (nF) RS (Ω) CF (pF) PHASE MARGIN (°)
0.5 680 10 17.4
1 680 20 12.4
1.5 680 30 10.1

The LMV641 is capable of driving heavy capacitive loads of up to 1 nF without oscillating, however it is recommended to use compensation should the load exceed 1 nF. Using this methodology will reduce any excessive ringing and help maintain the phase margin for stability. The values of the compensation network tabulated above illustrate the phase margin degradation as a function of the capacitive load.

Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth. The closed loop bandwidth of the circuit is now limited by RF and CF.

7.4.1.2 Compensation by External Resistor

In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the loop compensation is not viable. A simpler scheme for compensation is shown in Figure 38. A resistor, RISO, is placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability. The value of RISO to be used should be decided depending on the size of CL and the level of performance desired. Values ranging from 5Ω to 50Ω are usually sufficient to ensure stability. A larger value of RISO will result in a system with less ringing and overshoot, but will also limit the output swing and the short circuit current of the circuit.

LMV641 20203360.gif Figure 38. Compensation by Isolation Resistor