JAJSMF0B July 2021 – February 2024 LMX1204
PRODUCTION DATA
The LMX1204 has four main clock outputs and another LOGICLK output. The main clock outputs are all the same frequency. This frequency can be the same, divided, or multiplied relative to the input clock. Each of these clock outputs has programmable power level. The LOGICLK output frequency is independent and typically lower frequency than the other four main clocks and has programmable output format (CML, LVDS, LVPECL) and power level.
The SYSREF can be generated by either repeating the input from the SYSREFREQ pins, or internally generated. There is an internal SYSREF windowing feature that allows the internal timing of the device to be adjusted to optimize setup/hold times of the SYSREFREQ input with respect to the CLKIN input. This feature assumes that the delay between the SYSREF edge and the next rising clock edge is consistent. Each of the five outputs has a corresponding SYSREF output that has individual delays and programmable common mode. For the LOGISYSREF output, the output format is programmable as CML, LVDS, or LVPECL.