JAJSF76D September   2015  – June 2018 LMZ36002

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics
    7. 6.7  Typical Characteristics
    8. 6.8  Typical Characteristics
    9. 6.9  Typical Characteristics
    10. 6.10 Typical Characteristics (Thermal Derating)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Switching Frequency (RT)
      3. 7.3.3  Recommended Operating Range
      4. 7.3.4  Synchronization (CLK)
      5. 7.3.5  Output Capacitor Selection
      6. 7.3.6  VERSA-COMP Pin Configurations
      7. 7.3.7  Input Capacitor Selection
      8. 7.3.8  Output On/Off Inhibit (INH/UVLO)
      9. 7.3.9  Under Voltage Lockout (UVLO)
      10. 7.3.10 Remote Sense
      11. 7.3.11 VBSEL
      12. 7.3.12 Soft-Start (SS/TR)
      13. 7.3.13 Power Good (PWRGD) and Pull-up (PWRGD_PU)
      14. 7.3.14 Overcurrent Protection
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Minimum External Component Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
          1. 8.1.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.1.1.2.2 Output Voltage Set-Point
          3. 8.1.1.2.3 RT and RTSEL
          4. 8.1.1.2.4 VERSA-COMP
          5. 8.1.1.2.5 VBSEL
          6. 8.1.1.2.6 Input Capacitors
          7. 8.1.1.2.7 Output Capacitors
          8. 8.1.1.2.8 Application Curves
      2. 8.1.2 Typical Application
        1. 8.1.2.1 Design Requirements
      3. 8.1.3 Detailed Design Procedure
        1. 8.1.3.1 Switching Frequency
        2. 8.1.3.2 Power Good
        3. 8.1.3.3 Inhibit Control
        4. 8.1.3.4 VERSA-COMP
        5. 8.1.3.5 VBSEL
        6. 8.1.3.6 Soft-Start Capacitors
        7. 8.1.3.7 Input Capacitors
        8. 8.1.3.8 Output Capacitors
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
      2. 11.1.2 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over -40°C to +105°C free-air temperature, PVIN = 24 V, VOUT = 5 V, IOUT = IOUT(max), ƒsw = 500 kHz, CIN1 = 1 × 10-µF, 100-V 1210 ceramic, CIN2 = 1 × 100-µF 100-V electrolytic bulk, and COUT = 3 × 47-µF, 16-V 1210 ceramic (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (PVIN)
PVIN Input voltage range Over IOUT range 4.5(1) 60 V
UVLO PVIN undervoltage lockout PVIN increasing 3.2 3.8 V
PVIN decreasing 2.8 V
OUTPUT VOLTAGE
VOUT(ADJ) Output voltage adjust range Over IOUT range 2.5 7.5 V
VOUT Set-point voltage tolerance TA = 25°C, IOUT = 300 mA ±0.7% ±1.5(2)
Temperature variation -40°C ≤ TA ≤ 105°C, IOUT = 0 A ±0.9%
Line regulation TA = 25°C, Over PVIN range, IOUT = 300 mA ±0.1%
Load regulation TA = 25°C, IOUT = 300 mA to IOUT max ±0.3%
Total output voltage variation Includes set-point, line, load, and temperature ±2%
VOUT ripple Output voltage ripple 20-MHz Bandwidth 10% mV/pp
OUTPUT CURRENT
IOUT Output current TA = 105°C, natural convection 0 1.5 A
IOUT Output current TA = 105°C, 200LFM 0 2 A
IOUT Output current TA = 95°C, natural convection 0 2 A
ILIM Overcurrent threshold 2.5 A
PERFORMANCE
η Efficiency PVIN = 12 V
IOUT = 1 A		 VOUT = 7.5 V, ƒSW = 400 kHz 95%
VOUT = 5 V, ƒSW = 200 kHz 93%
VOUT = 5 V, ƒSW = 500 kHz 92%
VOUT = 3.3 V, ƒSW= 200 kHz 90%
VOUT = 2.5 V, ƒSW = 200 kHz 87%
PVIN = 24 V
IOUT = 1 A		 VOUT = 7.5 V, ƒSW = 400 kHz 92%
VOUT = 5 V, ƒSW= 250 kHz 90%
VOUT = 5 V, ƒSW= 500 kHz 88%
VOUT = 3.3 V, ƒSW = 250 kHz 86%
VOUT = 2.5 V, ƒSW = 250 kHz 81%
Transient response IOUT = 50% load step
1 A/µs slew rate		 Recovery time 100 µs
Over/Undershoot 2%
SLOW START
tSS Internal soft-start time SS/TR pin open 4.1 ms
INHIBIT
VINH (high) Inhibit control Precision inhibit level 2.00 2.1 2.42 V
VINH (hys) Inhibit turn-off hysteresis –0.294 V
II (shutdown) Input shutdown supply
current		 INH/UVLO pin conected to AGND 2.4 6.2(3) µA
POWER GOOD (PWRGD)
VPWRGD PWRGD thresholds VOUT rising Good 95%
Fault 110%
VOUT falling Fault 90%
Good 105%
THERMAL SHUTDOWN
TSHUTDOWN Thermal shutdown Shutdown Temperature 160 °C
Hysteresis 10 °C
INPUT/OUTPUT CAPACITANCE
CIN External input capacitance ceramic 10(4) µF
non-ceramic 100 µF
COUT External output capacitance Ceramic 64(5) Note(6) µF
Non-ceramic 100 Note(6) µF
ceramic + non-ceramic Note(6) µF
Equivalent series resistance (ESR) 20 mΩ
(1) The minimum PVIN is 4.5 V or (VOUT / 0.75), whichever is greater. For VOUT = 3.3 V, the minimum PVIN is 4.75 V when IOUT > 1.5 A.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance is affected by the tolerance of the external RSET resistor.
(3) Specified by design. Not production tested.
(4) The specified minimum ceramic input capacitance represents the standard capacitance value. The actual effective capacitance after considering the effects of DC bias and temperature variation should be ≥ 4.7 µF.
(5) The amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection). The minimum required output capacitance must be comprised of ceramic capacitance. The amount of required ceramic capacitance represents the standard capacitance value. Locate the capacitance close to the device. Adding additional ceramic or non-ceramic capacitance close to the load improves the response of the regulator to load transients.
(6) The maximum allowable output capacitance varies depending on the output voltage (see Output Capacitor Selection).